A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature- and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 μm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm² consumes 16 μW at 8 kS/s and 2.5 V.     

A 0.35μm CMOS Mixer for 2.45-GHz RFID Application

A RF mixer with both low noise and high linearity is designed,operating at 2.45-GHz ISM band for RFID application.The designed mixer uses an optimal input matching network and the carefully chosen sizes of transistors,also with the appropriate bias point,to improve the noise figure(NF).Also,with a resonant LC loop as the current source and a parallel PMOS-resistor as the load,the mixer has a high linearity.The post simulation results show that the single side- band noise figure of 8.57 dB,conversion gain of 10.02 dB,input 1-dB compression point(P-1dB)of-8.33 dBm,and input third-order intercept point(IIP3)of 5.35 dBm.     

A 20MHz Low Phase-Noise 0.35μm CMOS Crystal Oscillator

The design procedure of a CMOS process integrating Colpitts crystal oscillator is described in detail by using the tools of Matlab and advanced design system (ADS). The small-signal analysis is performed both in the viewpoint of negative resistance and positive feedback. The analysis of condition for reliable start-up of oscillation and design guides for low phase noise is introduced The measured phase noise is -172dBc/Hz@10 kHz and the power dissipation is 0.36 mW at power supply 3 V.     

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.     

0.35μm CMOS激光二极管驱动器的设计

本文介绍了0.35μm CMOS工艺的激光二极管驱动器集成电路的设计。整个电路用Smart Spice模拟，模拟结果显示工作速率可以达到2.5Gb/s，调制电流幅度可以达到50mA以上，并且可以通过调节电压Vmod使调制电流幅度在0到50mA之间变化。     

一种基于0.35μm CMOS工艺的14位100MSPS DAC设计

基于 TSMC 0 .3 5μm CMOS工艺设计了一种工作电压为 3 V/ 5 V的 1 4位 1 0 0 MSPS DAC。 1 4位DAC在 5 0 Ω负载条件下满量程电流可达 2 0 m A,当采样速率为 1 0 0 MHz时 ,5 V电源的满量程条件下功耗为1 90 m W,而 3 V时的相应功耗为 45 m W该 DAC的积分非线性误差 ( IN L )为± 1 .5 LSB,微分非线性误差( DN L)为± 0 .75 LSB。在 1 2 5 MSPS,输出频率为 1 0 MHz条件下的无杂波动态范围 ( SFDR)为 72 d Bc。     

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB.     

0.35μm SOI CMOS器件建模技术研究

介绍了SOI技术的优势和器件建模的意义.针对0.35μmSOI CMOS工艺的开发,设计了用于建模的测试芯片.对于SOIMOSFET中存在的自加热等寄生效应设计了参数提取的流程,并设计了相应的测试方法.在得到所需的测试数据后,采用局部优化方法进行参数提取.最后通过模型仿真结果和测试数据的比较证明了建立的0.35μm SOI CMOS模型有较高的精度.     

2.9GHz 0.35μm CMOS低噪声放大器

随着特征尺寸的不断减小,深亚微米CMOS工艺其MOSFET的特征频率已经达到50Hz以上,使得利用CMOS工艺实现GHz频段的高频模拟集成电路成为可能,越来越多的射频工程师开始利用先进的CMOS工艺设计射频集成电路,本文给出了一个利用0．35μmCMOS工艺实现的2．9GHz单片低噪声放大器,放大器采用片内集成的螺旋电感实现低噪声和单片集成。在3伏电源下,工作电流为8mA,功率增益大于10dB,输入反射小于－12dB.     

2.4GHz 0.35μm CMOS Gilbert下变频器

利用0 35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器.其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2 452GHz,2 45GHz和2MHz.测试表明:在3 3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为-11dBm.     

0.35μm CMOS多晶硅栅刻蚀工艺研究

本文主要研究0.35μm CMOS多晶硅栅刻蚀工艺中“硅LOSS”及“T腰”问题的形成机理.在不改变产品工艺流程的前提下,对多晶硅栅刻蚀工艺进行优化,提出“两步ME法”优化了刻蚀形貌,改善了硅LOSS、T腰的问题.满足0.35μm CMOS多晶形貌及工艺要求,具有一定的理论指导和实际意义.     

A High-Performance Doubly-Balanced Mixer in 0.35-μm CMOS for Mode-1 MB-OFDM UWB Receivers

A new design of CMOS doubly-balanced down-conversion mixer intended for Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) receiver of UWB group#1 bands and optimized for 0.35-μm technology is presented. The proposed mixer uses the current-bleeding technique in both the driver and switching stages with wideband impedance matching, consisting of a bandpass filter embedding the RF stage. The mixer performances are optimized for the AMS 0.35 μm CMOS process parameters. Over 3.1–4.8 GHz, the circuit drawing 6 mA from 3-V supply, shows a conversion gain of 14.0±1.0 dB, IIP3 of 0±2 dBm, doubly-sideband noise figure of 4.5–4.8 dB, and port-to-port isolation above 61.0 dB.

0.35/0.5μm CMOS光接收电路设计研究

对一种结构简单的互阻ＣＭＯＳ放大器的工作原理进行了分析,着重对其灵敏度、频率特性和动态范围等参数与电路结构参数之间的关系进行了模拟分析和设计研究。接收电路按０．３５／０．５μｍ规则设计,在采用０．８μｍ沟道长度的条件下,电路工作频率可达６００Ｍｂ／ｓ,允许最小输入光电流约为５μＡ,光电流噪声抑制能力可通过前两级放大器的宽长比来调节。     

A novel 2.2 Gbps LVDS driver circuit design based on 0.35μm CMOS

This paper presents a novel high-speed low voltage differential signaling(LVDS) driver design for point-to -point communication.The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased.A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage.The proposed driver was implemented in a standard 0.35μm CMOS process with a die area of 0.15 mm~2.The test result show...     

A readout IC for an uncooled microbolometer infrared FPA with on-chip self-heating compensation in 0.35 μm CMOS

This paper describes a readout integrated circuit architecture for an infrared focal plane array intended for infrared network-attached video cameras in surveillance applications. The focal plane array consists of 352 × 288 uncooled thin-film microbolometer detectors with a pitch of 25 μm, enabling ambient temperature operation. The circuit features a low-noise readout path, detector resistance mismatch correction and a non-linear ramped current pulse scheme for the electrical biasing of the detectors in order to relax the dynamic range requirement of amplifiers and the ADC in the readout channel, imposed by detector process variation and self-heating during readout. The design is implemented in a 0.35-μm standard CMOS process and two versions of a smaller 32 × 32-pixel test chip have been fabricated and measured for evaluation. The latest test chip achieves a dynamic range of 97 dB and an input-referred RMS noise voltage of 6.4 μV yielding an estimated NETD value of 26 mK with f/1 optics. At a frame rate of 60 FPS the chip dissipates 170 mW of power from a 3.4 V supply.     

一种2.4GHz 0.35μm CMOS Gilbert下变频器

利用0.35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器．其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2.452GHz,2.45GHz和2MHz．测试表明：在3.3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为－11dBm．     

16信道0.35μm CMOS/VCSEL光发射模块

研究了垂直腔面发射激光器(VCSEL)及其列阵器件的光谱特性、调制特性、高频特性及与微电子电路的兼容性,将1×16的VCSEL与CMOS专用集成电路进行多芯片组装(MCM),混合集成为16信道VCSEL光发射功能模块.测试过程中,功能模块的光电特性及其均匀性良好,测量的-3dB频带宽度大于2GHz.