2D analytical calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunneling/thermionic current

In this paper we present a new approach to calculate the channel electric field within a Schottky barrier Double-Gate MOSFET (SB-DG-MOSFET) in subthreshold region by solving Poissons equation. The Poisson equation is solved two dimensionally in an analytical closed-form with the conformal mapping technique. A comparison with data simulated by TCAD Sentaurus simulator for channel lengths down to 22 nm was made and shows an accurate agreement. Futhermore, a new way for the estimation of the tunneling current in SB-DG-MOSFET by applying the above 2D solution for the electric field and a 2D solution of the electrostatic potential is presented. Calculating the tunneling current, we use Wentzel-Kramers-Brillouin (WKB) approximation for the estimation of the tunneling probability. For the calculation of the tunneling and thermionic current a comparison with TCAD Sentaurus for channel lengths down to 65 nm was made.     

Analytical Modeling of Source-to-Drain Tunneling in Nanoscale Silicon MOSFET

Sub-10-nm bulk n-MOSFET(metal-oxide-semiconductor field effect transistor) direct source-todrain tunneling current density using Wentzel-Krammers-Brillouin(WKB) transmission tunneling theory has been simulated.The dependence of the source-to-drain tunneling current on channel length and barrier height is examined.Inversion layer quantization,band-gap narrowing,and drain induced barrier lowering effects have been included in the model.It has been observed that the leakage current density increases severely below 4 nm channel lengths,thus putting a limit to the scaling down of the MOSFETs.The results match closely with the numerical results already reported in literatures.     

Impact ionization in InAlAs/InGaAs/InAlAs HEMT's

The kink effect and excess gate current in InAlAs/InGaAs/InAlAs HEMT's have been linked to impact ionization in the high field region of the channel. In this letter, a relationship is established between experimentally measured excess gate current and the tunneling of holes from the quantum well formed in the channel. The channel hole current is then obtained as the quotient of the excess gate current to the gate-voltage-dependent transmission probability. This channel hole current follows the exponential dependence of the ionization constant on the inverse electric field     

GaN HFET的沟道夹断特性和强电场下的电流崩塌

从自洽求解二维泊松方程和薛定谔方程出发,研究了纵、横向电场作用下GaNHFET沟道中的电子态和夹断特性。建立了不同异质结构和电场梯度下的电荷控制模型;运用热电子隧穿电流崩塌模型解释了强场电流崩塌的实验结果;强调了沟道夹断特性对电流崩塌的影响;研究了背势垒异质结构、场板电极和挖槽等抑制电流崩塌的方案,提出利用挖槽独立设计内、外沟道异质结构抑制强场电流崩塌的新思路。     

超薄栅介质MOSFET直接隧穿电流自洽解模型

采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿 (S/ D tunneling) ,采用 WKB方法计算载流子源漏隧穿几率 ,对薄硅层(硅层厚度为 1nm) DG(dual gate) MOSFETs的器件特性进行了模拟 .模拟结果表明当沟道长度为 10 nm时 ,源漏隧穿电流在关态电流中占 2 5 % ,在开态电流中占 5 % .随着沟道长度进一步减小 ,源漏隧穿比例进一步增大 .因此 ,模拟必须包括源漏隧穿 .     

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.      

GaN HFET沟道热电子隧穿电流崩塌模型

研究了GaN HFET中沟道热电子隧穿到表面态及表面态电子跃迁到表面导带两种跃迁过程及其激活能.从沟道热电子隧穿过程出发,提出了新的电流崩塌微观模型.用该微观模型解释了光离化谱、DLTS、瞬态电流及电流崩塌等各类实验现象.研究了各种异质结构的不同电流崩塌特性,在此基础上讨论了无电流崩塌器件的优化设计.     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

微波功率AlGaN/GaN HFET的二维能带和异质结构设计

在综述微波功率AlGaN/GaN HFET技术发展趋势基础上,提出了二维异质结能带优化设计的新课题.从自洽求解薛定谔方程和泊松方程出发研究了利用异质界面上的极化电荷来剪裁异质结能带.用极化电荷设计近矩形前势垒能增大高能热电子的隧穿势垒宽度,抑制电流崩塌.背势垒中的极化电荷强化了沟道阱的量子限制,减弱了沟道中的强场峰,能提高击穿电压和抑制电流崩塌.薄势垒层中的极化电荷强化了沟道阱的结构,降低势垒高度后能产生高密度的电子气.优化设计二维异质结构能抑制沟道中的强场峰和电流崩塌,提高击穿电压和大漏压下的输出功率.     

Drain-avalanche and hole-trapping induced gate leakage inthin-oxide MOS devices

Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 Å) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10¹⁶ to 10¹⁷ cm^-3. For oxides thicker than 110 Å, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 Å the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide     

First-principles study of the effects of oxygen vacancy on hole tunneling current

The effects of oxygen vacancies on the electronic structure of silicon dioxide and the hole tunneling current were investigated using first-principles calculations. A level related to oxygen vacancy was obtained to be nearly 2.0 eV from the top of valence band within the bandgap of the α-quartz supercell with one oxygen vacancy. And therefore the defect assisted hole (electron) tunneling currents were calculated. The results shows that the hole tunneling current will be dominant for a thinner oxide thickness at low oxide field and the contribution of trap assisted hole tunneling to the total tunneling current decreases with oxide thickness and oxide field increasing. It is concluded that the effects of the oxygen vacancies on the hole tunneling current become smaller with larger oxide thickness and higher electric field.     

Fabrication of asymmetric Ge Schottky tunneling source n-channel field-effect transistor and its characterization of tunneling conduction

An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short channel effect and to reduce the off-state current. An obstacle to implement a STS FET with a high mobility Ge channel was to form a metal/Ge contact with a low electron barrier height (Φ_BN). Recently, we succeeded in the fabrication of a TiN/Ge contact with an extremely low Φ_BN. In this study, a Ge-STS n-channel FET was fabricated, here PtGe/Ge and TiN/Ge contacts were used as the source and the drain. The device showed well-behaved transistor operation. From the current-voltage measurements in the wide temperature range of 160–300 K, the conduction mechanism from the source to the channel is confirmed to be field emission tunneling. This result will be the first step toward achieving a high-performance Ge-STS n-FET.     

An analytic three-terminal band-to-band tunneling model on GIDL inMOSFET

An analytic three-terminal band-to-band tunneling current model for the gate-induced drain leakage current (GIDL) in an n-MOSFET is developed. This model considers impurity doping concentration, vertical field, lateral field, and so-induced electron momentum enhancement, as well as the surface electro-static potential in the gate-to-drain overlapped region. Based on a constant surface-potential approximation, a closed-form equation has been obtained instead of the complex integral-form in previous works. The results from this new model show good agreement with the measurement data over a wide range of gate and drain biases and device channel lengths. This work is useful for GIDL analysis in transistor design as well as in circuit simulation     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

Stress induced leakage current analysis via quantum yieldexperiments

This paper investigates the physical characteristics of stress induced leakage current (SILC) by means of quantum yield (QY) measurements and simulations. QY experiments allow us to infer the energy of tunneling electrons, which is an important factor for the damage generation process. The energy of SILC electrons is analyzed in three different types of p-MOSFET devices: n⁺ gate surface channel and buried channel, and p⁺ gate surface channel. We show that an extra tunneling current component due to native traps can be present even in virgin devices and it is elastic. Then it is shown that SILC electrons have less energy than direct tunneling electrons. This energy loss is then extracted from experimental data and the limitations of this extraction technique are addressed. Finally, experiments on p⁺ gate p-MOSFET clearly demonstrate that electrons tunneling through traps created by electrical stress lose energy irrespective of their initial band. It is then concluded that native and stress induced traps have different physical characteristics     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

Large enhancement of interband tunneling current densities of over105 A/cm2 inIn0.53Ga0.47As-based surface tunnel transistors

In_0.53Ga_0.47As-based Surface Tunnel Transistors (STT's), which control an interband tunneling current between an n-type channel and a p-type drain by an insulated gate, are investigated with the goal of increasing the tunneling current-density for high-speed operation. The fabricated devices enhanced an interband tunneling current density by a factor of 10² compared to the conventional GaAs-STT's due to a smaller bandgap energy and a lighter electron effective mass, and exhibited a clear gate-controlled negative differential resistance (NDR) characteristics with maximum tunneling current densities of over 10⁵ A/cm². The cutoff frequency (F_T) and maximum oscillation frequency (f_max ) of a fabricated device with a 1.0-μm gate length were estimated to be 7.9 GHz and 20 GHz, respectively, in the NDR region