An Agile, Ultra-Wideband Pulse Radio Transceiver With Discrete-Time Wideband-IF

A pulse-based CMOS ultra-wideband transmitter and receiver have been realized using a standard digital 90 nm CMOS process. The transceiver uses digital templates stored in high-speed memories for pulse generation on the transmit side and for correlation on the receive side. This allows fast band switching for multi-band operation and interferer avoidance without the requirement for fast-settling phase-locked loops. The receiver contains a 3.1–9.5 GHz broadband front-end and discrete-time intermediate frequency correlators that achieve a pulse rate of 100 Mpulses/s and has a die area of 1 ${hbox{mm}}^{2}$ while consuming 130 mA from a 1.2 V supply. The transmitter uses interleaved, intermediate frequency digital-to-analog converters followed by partial-order hold reconstruction filters that eliminate sampling images, and a quadrature RF up-converter. 1.25 nJ is spent per transmitted pulse for a pulse-repetition rate of 100 MHz while achieving a broadband image cancellation of 42 dB.      

High-Voltage High-Efficiency Ultrawideband Pulse Synthesizer

A novel ultrawideband pulse synthesizer based on distributed amplifier topology is presented. The basic concept is to combine different delayed Gaussian pulses with both positive and negative polarities to form an UWB pulse. Compared to other ultrawideband pulse-formation methods, this method can have both high-efficiency and high-voltage output. The prototype circuit based on 0.25-$mu$m pHEMT transistors is fabricated, and the fabricated pulse synthesizer consumes only 1-mA current under 5-V power supply with high energy efficiency of 10.1% at 10-MHz pulse repetition frequency (PRF). Measurement results show that with 1.5 -V amplitude and 240-ps Gaussian input pulse, the output pulse of the designed UWB pulse synthesizer is centered at 4 GHz with 4.5-V peak to peak amplitude (into 50-ohms load) and 1.0-ns duration at 50% of the peak pulse envelope.      

一种面向软件无线电的高速CDMA-VSAT收发信机

以软件无线电思想为基础,采用非相干解扩解调、M元扩频等技术,提出了一种同时传输两个物理信道,实现快速同步捕获和高速信息传输的CDMA-VSAT收发信机的新设计方案。这种收发信机可用单片DSP和FPGA实现,结构简单、设计灵活、可扩展性强,为VSAT网中的一些高速业务的应用奠定了基础。     

Energy Conversion Efficiency in an Ultrawideband Pulse Emitter

Journal of Communications Technology and Electronics - A calculation model of a plane aperture with nonuniform asynchronous excitation is constructed. The calculated results are in good agreement...     

Transceiver Module of Ultrawideband Polarization Radar for Sensing Objects behind a Wall

Journal of Communications Technology and Electronics - A transceiver system consisting of scanning receiving and transmitting antenna arrays is developed to study the detection of objects and...     

一种软件无线电台的设计

软件无线电(Software Radio)是以开放体系结构为基础,在硬件平台上应用软件工程技 术来实现具有最大灵活性和适应性的各种无线通信方式和功能的系统。介绍了一种软件无线电跳频电 台的设计,重点概述了总体方案。以接收机为对象分析了中频数字化、宽带射频电路、频率合成器,并适 当地给出了设计和计算。     

基于软件无线电技术的电台自动测试系统

文章介绍了一种基于软件无线电技术的多制式电台测试系统。该系统采用了直接射频采样,以硬件实现实时数字下变频与上变频,以软件在零中频信号上实现多制式调制解调的结构,从而可应用于对多制式电台的性能参数自动测量。     

A New Transceiver Architecture for the 60-GHz Band

A new “half-RF” architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90 $^{circ}$ phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7–7.1 dB and gain/phase mismatch of 1.1 dB/2.1$^{circ}$ while consuming 36 mW. The transmitter produces a maximum output level of $-$7.2 dBm and an image rejection of 20 dB while drawing 78 mW.      

软件无线电收发信机的设计实现

当今通信技术由模拟式向数字式、软件化方向快速发展,在此介绍了一种基于软件无线电技术的无线收发信机系统设计方案。其中采用了Intersil公司全数字上变频器HSP50415、全数字下变频器HSP50214B、数字科斯塔司环HSP50210与单片机AT89S8252、数字信号处理芯片TMS320VC5409及可编程逻辑器件EP1K30等构成系统的核心处理单元,通过软件实现对信号的无线收发。     

超宽带高功率电磁脉冲天线的设计与实验

在对近辐射场动力学过程辐射的研究基础上，提出能辐射超宽带电磁脉冲的综合天线的概念及天线试验研究的结果。研制此天线利用了能量应用这种概念，其有小的尺寸，高的电场强度，线极化辐射脉冲的中心形曲线图，并且完全适合作为扫描天线阵扫描单元。此天线由高压双极性脉冲发生器激励。     

一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器．该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串／串并转换电路、线驱动器和均衡器组成．为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构．电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm．经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好．     

一种单芯片无线收发系统设计

为了使无线收发系统能方便地应用于无线传感器网络、蓝牙技术与无限局域网（WLAN）等领域,采用了片上系统设计方法,将无线收发系统设计在一块单芯片上,使其最小化。给出了单芯片无线电的基本结构及电路实现的若干组成部分（混频器,低噪音放大器,功率放大器等）的解决方案。电路具有体积小,低功耗,成本低,可靠性高的特点。     

一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器.该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串/串并转换电路、线驱动器和均衡器组成.为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构.电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm.经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好.     

UF0MC-IOTA Based Cognitive Radio Transceiver

Wireless Personal Communications - Express evolution in smart wireless communication address the issue of spectrum scarcity. Implementation of cognitive radio (CR) is one of the promising...     

A Space-Time Coded MIMO TH-UWB Transceiver with Binary Pulse Position Modulation

In this paper, we propose a new multiple-input- multiple-output (MIMO) transceiver for time-hopping ultra- wideband (TH-UWB) communications. We consider the problem of space-time (ST) coding with binary pulse position modulation (PPM) and we propose the first known family of rate-1 ST codes that can be associated with binary PPM without introducing any additional constellation extension. We prove that the proposed encoding scheme can achieve a full transmit diversity order with 2^k transmit antennas. At the receiver side, we propose a maximum-likelihood (ML) decoder that is adapted to the structure of the considered multi-dimensional constellation that does not have the structure of a lattice.     

5cm超小型脉冲相参收发系统

介绍了一种超小型的５ｃｍ脉冲相参接收发射机的设计方案和实验结果,以及在５ｃｍ箭载电子设备中的应用。     

单片射频发射接收芯片GJRF400的应用

本文介绍了射频发送接收芯片－GJRF400的结构，并细述了其编程方法和应用中应注意的问题。     

A Single Sideband RF-Modulator for Digital-IF Transmitter

The limitation of the single-sideband rejection ratio (SSRR) performance of transmitters based on I/Q mismatching due to high frequency signals has been investigated. The proposed single-sideband radio frequency-modulator (SSM) is capable of generating a single sideband frequency without implementing a quadrature local oscillator which displaces a phase of a local oscillating signal by 90$^{circ}$ at a high frequency. This technique is promising for radio transmission with a SSRR of more than 60 dBc. Also, the architecture of digital-intermediate frequency transmitter using the proposed SSM can be applied for a future software-defined radio solution supporting multiband and multimode wireless communications.      

WiMax终端收发系统结构分析

概述IEEE802.16/wiMax规范及演变, 对IEEE802.16/WiMax的射频接收器的结构和性能进行了系统分析,并介绍了几种芯片组的解决方案.