High speed GaAs integrated circuits

Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.     

GaAs MESFET logic with 4-GHz clock rate

Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.     

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.     

CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications

Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.     

A self-aligned gate III-V heterostructure FET process forultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8×8 multiplier/accumulator, and a 4500-gate 16×16 complex multiplier have been demonstrated using enhancement-mode n⁺ -(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-μm gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 μm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained     

A gigabit MOS logic circuit with buried channel MOSFETs

An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.     

A picosecond-accuracy, 700-MHz range, Si bipolar time intervalcounter LSI

A picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems is described. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5 K gate array LSI by developing fully digitally processes heat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, ±3-ps linearity, zero-skew offset of ±2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz     

A high-speed LSI GaAs 8/spl times/8 bit parallel multiplier

Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.     

A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

Direct measurement of picosecond propagation delays in individual logic gates by a differential optoelectronic technique

We describe the first direct measurement of single-gate propagation delays in gigabit GaAs digital IC's. Our technique uses picosecond light pulses to generate short on-chip logic-level-switched pulses and infers single logic gate delays by differential measurement of output waveforms. In the ∼ 2-GHz clock-rate D-flip-flop selected for these measurements, single-gate propagation delays of ∼ 100 ps were measured in specific NOR gates internal to the flip-flop (FF) with this new measurement technique; the technique is easily extendible to measurement of gate delays of the order of a few picoseconds.     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

The Future Impact of GaAs Digital IC's

A review of digital GaAs IC technology and an assessment of its future impact on gigabit signal processing is presented. High-speed signal processing and computers will require MSI-complexity interface circuits capable of 1-10 GHz clock frequencies and LSI-complexity digital circuits operating in the 0.2-5 GHz range at tens of microwatts per gate. A wide range of applications exists for frequency counters, multiplexers, A/D converters, FFT's, microprocessors, and memories that operate at speeds significantly higher than on presently available circuits. Issues related to high-speed IC design such as power dissipation, packing density, capacitance effects, design rules, and intra- and interchip propagation delays are discussed.     

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One circuit uses a seven-stage shift register operating with a half-rate clock and provides output signals up to 100 Gb/s. The second circuit contains an eleven-stage shift register operating with a full-rate clock up to 54 Gb/s. Both PRBS generators provide a wide range of data rates down to below 1 Gb/s simply by changing the frequency of the external clock signal without the need of any further adjustments. The integrated circuits provide a trigger output which can be switched between eye and pattern display. Furthermore, they contain additional circuitry to guarantee automatic start after power-on. The circuits are manufactured in a 200-GHz f/sub T/ SiGe bipolar technology. They each have a chip size of 900/spl times/700 /spl mu/m/sup 2/ and consume 1.5 and 1.9 W, respectively.     

Application of MoSi/sub 2/ to the Double-Level Interconnections of I/sup 2/L Circuits

A new MoSi/sub 2/-CVD-Al double-level interconnection system is developed to obtain a high packing density in I/sup 2/L circuits. Taking advantage of MoSi/sub 2/, a fine pattern consisting of a Iinewidth of 2.5 /spl mu/m aid a spacing of 1 /spl mu/m is achieved for the first-level interconnections. This new system has a higher reliability than the normaf Al-CVD-Al structure because of the stability of the MoSi2 surface. The fundamental properties of 1/sup2/L gates with MoSi2 interconnections, namely, gain, propagation delay time, and toggle frequency of a T flip-flop, are measured. At practical injector currents, they show nearly the same values as with Al interconnectiorm The resistance effects of MoSi/sub 2/ interconnections are calculated with regard to the unbalance of the injector currents and increase of the propagation delay time. The calculations show that these effects can be ignored at an injector current of 1 /spl mu/A/gate. At higher injector currents, the MoSi/sub 2/ interconnection resistance must be taken into account in I/sup 2/L pattern layout.     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

AC-and DC-powered subnanosecond 1-kbit Josephson cache memorydesign

The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators