Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.     

A Novel Frequency Compensation Technique for Three-Stage Amplifier

Multistage amplifiers are urgently needed with the advance in technology, due to the fact that single-stage cascode amplifier is no longer suitable in low-voltage designs. Moreover, the short-channel effects of the sub-micro CMOS transistor cause output-impedance degradation and hence the gain of an amplifier is reduced dramatically[1~6]. For multistage amplifiers, most of the compensation methods are based on pole splitting and pushing the right-half-plane zero to high frequencies or pole-ze…     

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.     

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.     

Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.     

Positive feedback frequency compensation for low-voltage low-power three-stage amplifier

The use of a new frequency compensation scheme for a three-stage operational amplifier is presented. The use of a positive feedback compensation (PFC) is employed to improve frequency response when compared to nested Miller compensation. A set of design equations is derived to give insight into the sizing of the amplifier. In addition, some characteristics relevant to the low-voltage low-power circuits using operational amplifiers have been modeled. Finally, an optimization algorithm was used with the purpose of extracting the most efficient solution. The PFC is especially suitable for driving large capacitance loads. It improves frequency response, slew rate (SR), and settling time. Small compensation capacitors make it appropriate for integration in commercial CMOS processes. With an active area of 0.03 mm/sup 2/ and working at 1.5 V, the circuit dissipates 275 /spl mu/W, has more than a 100-dB gain, a gain bandwidth of 2.7 MHz, and 1.0 V/spl mu/s average SR while driving a 130-pF load. Both measured frequency and transient step response show that the amplifier is stable.     

A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path

A micropower chopper stabilized opamp is presented. The new topology incorporates a switched capacitor filter with synchronous integration inside the continuous time signal path virtually eliminating chopping noise. A three-stage amplifier with multipath nested Miller compensation is modified to incorporate chopping of the input stage, sinc filtering to notch any chopping ripple, and a compensation scheme to maintain an undistorted high-speed signal path. Characteristics of the amplifier presented include rail to rail input and output operating on supplies of 1.8 to 5.5 V over -40degC to 125degC. Quiescent supply current is 17 muA, input offset is 3 muV, input offset drift is 0.02 muV/degC, GBW is 350 kHz, and the chopping frequency is 125 kHz. Die area is 0.7 mm² using a precision analog mixed-signal CMOS process combining low-noise 0.6-mum analog transistors with 0.3-mum digital CMOS capability     

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6-/spl mu/m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%.     

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 μm process parameters. The ac simulation results of amplifier show that GBW is 9 MHz and power consumption is 0.5 mW.     

A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-μm CMOS technology. Qiang Li received the B.S. degree and the M.Sc. degree in College of Microelectronics and Solid-state Electronics from University of Electronic and Technology Science of China (UESTC), in 2002 and 2005, respectively. His main research interest is low-voltage low-power analog ICs and power switch management ICs. From 2005, he joined the o2micro as an analog IC designer. Jun Yi un Yi received the B.S. degree and the M.Sc. degree, both in Microelectronics, from University of Electronic Science and Technology of China, Chengdu, China, in 2001 and 2004, respectively. He is currently working toward the Ph.D. degree at The Hong Kong University of Science and Technology, Hong Kong, China. His research interests include low-voltage low-power analog and mixed-signal integrated circuits, low-power power management system, with current emphasis on ultra-low-power power management and signal processing integrated circuits for micro-sensor, RFID, and biomedical applications. Bo Zhang was born in Chongqing, China, on May 26, 1964. He received his B. Tech. degree in electronic engineering from Beijing Institute of Technology, China in 1985, the M. Tech. degree from the University of Electronic Science and Technology of China in 1988. From 1988 to 1996, he worked on power semiconductor devices research and development at the University of Electronic Science and Technology of China. From 1996 to 1999, he was a Visiting Professor at Virginia Polytechnic Institute and State University, Blacksburg, U.S.A., where his research activities include device simulations, power semiconductor cryogenics, SiC power devices, and other Si-based power semiconductor devices. Since returning to the University of Electronic Science and Technology, China, in Nov. 1999, he has worked on power devices and smart power ICs. He is currently a Professor and has published more than 100 papers in the international conferences and journals. Zhaoji Li, professor, the director of IC design center of University of Electronic Science and Technology of China (UESTC).     

Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads

In this paper, a dual-Miller parallel compensation (DMPC) technique for low-power three-stage amplifier is presented with detailed theoretical analysis. A feedback network realized by capacitor and transconductance is added between the first and third stage, which improves significantly the performance when driving large capacitive loads. Furthermore, it is found to be stable for a wide range of capacitive loads. The proposed DMPC amplifier has been implemented in a 0.13-μm CMOS process and the chip area is 0.17×0.11 mm². It achieves a 0.87 MHz gain-bandwidth product by consuming a total current of 41 μA. The DMPC amplifier is verified to be stable when the load capacitor ranges from 8 pF to 2 nF.     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.     

用于低功耗三级放大器的嵌套式密勒有源电容频率补偿技术

提出了一种新的用于低功耗,节省面积的三级放大器频率补偿技术.该技术将有源电容进行嵌套连接从而克服了传统的嵌套式密勒补偿与反嵌套式密勒补偿的缺点.当将这一技术用标准的0.35μm工艺设计成电路并负载150pF电容时,放大器实现了105dB直流增益,3.3M的增益带宽积,68°相位裕度以及2.56V/μs的平均转换速率.而这一切的实现是在2V电源电压仅消耗40μW的功耗以及使用了很小的补偿电容.     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

Three-stage large capacitive load amplifier withdamping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-μm CMOS process with V_tn=0.72 V and V_tp=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51° phase margin, 0.33-V/μs slew rate, 3.54-μs settling time, and 426-μW power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.