SOI-DRAM circuit technologies for low power high speed multigigascale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

A 5-V-only operation 0.6-μm flash EEPROM with row decoder schemein triple-well structure

An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm² has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm², and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm² by using the minimal cell size (2.0×10 μm²)     

Scaled dielectric antifuse structure for field-programmable gatearray applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×10¹² s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N⁺ antifuse structures     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

Low-operation voltage of InGaN/GaN light-emitting diodes by using aMg-doped Al0.15Ga0.85N/GaN superlattice

Low-resistivity Mg-doped Al_0.15Ga_0.85N/GaN strained-layer superlattices were grown. In these superlattices, the maximum hole concentration is 3×10¹⁸/cm³ at room temperature. Hall-effect measurements indicate high conductivity of this structure in which the high activation efficiency is attributed to the strain-induced piezoelectric fields. This work also fabricated InGaN/GaN blue LEDs that consist of a Mg-doped Al_0.15Ga_0.85N/GaN SLs. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 3 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V     

Low-operation voltage of InGaN-GaN light-emitting diodes withSi-doped In0.3Ga0.7N/GaN short-period superlatticetunneling contact layer

InGaN/GaN multiple-quantum-well light-emitting diode (LED) structures including a Si-doped In_0.23Ga_0.77N/GaN short-period superlattice (SPS) tunneling contact were grown by metalorganic vapor phase epitaxy. In_0.23Ga_0.77N/GaN(n⁺)-GaN(p) tunneling junction, the low-resistivity n⁺-In_0.3Ga_0.77 N/GaN SPS instead of high-resistivity p-type GaN as a top contact layer, allows the reverse-biased tunnel junction to form an “ohmic” contact. In this structure, the sheet electron concentration of Si-doped In_0.23Ga_0.77N/GaN SPS is around 1×10¹⁴/cm², leading to an averaged electron concentration of around 1×10²⁰/cm³. This high-conductivity SPS would lead to a low-resistivity ohmic contact (Au/Ni/SPS) of LED. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 2.95 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V     

A 3.8-ns 16 K BiCMOS SRAM

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

Carrier transport related analysis of high-power AlGaN/GaN HEMTstructures

Shubnikov-de Haas (SdH) oscillation and Hall measurement results were compared with HEMT DC and RF characteristics for two different MOCVD grown AlGaN-GaN HEMT structures on semiinsulating 4H-SiC substrates. A HEMT with a 40-nm, highly doped AlGaN cap layer exhibited an electron mobility of 1500 cm²/V/s and a sheet concentration of 9×10¹² cm at 300 K (7900 cm²/V/s and 8×10¹² cm^-2 at 80 K), but showed a high threshold voltage and high DC output conductance. A 27-nm AlGaN cap with a thinner, lightly doped donor layer yielded similar Hall values, but lower threshold voltage and output conductance and demonstrated a high CW power density of 6.9 W/mm at 10 GHz. The 2DEG of this improved structure had a sheet concentration of n_SdH=7.8×10¹² cm^-2 and a high quantum scattering lifetime of τ_q=1.5×10^-13 s at 4.2 K compared to n_SdH=8.24×10¹² cm^-2 and τ_q=1.72×10^-13 s for the thick AlGaN cap layer structure, Despite the excellent characteristics of the films, the SdH oscillations still indicate a slight parallel conduction and a weak localization of electrons. These results indicate that good channel quality and high sheet carrier density are not the only HEMT attributes required for good transistor performance     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitlinedirect sensing scheme

A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-μm triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 μm² , the smallest yet reported for 0.25-μm CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²     

Effects of buried layer geometry on characteristics of doublepolysilicon bipolar transistors

Dependences of electrical characteristics of double polysilicon transistors on n⁺ buried islands (subcollector) are examined. By simply modifying layouts of the buried island, the Early voltage (V _A), collector-to-emitter breakdown voltage (BV_CEO), and β×V_A product of transistors are increased from 42, 5.6, and 3070 V to 61, 6.7, and 3820 V, respectively, while the peak cutoff frequency at a V_CE of 1.5 V is decreased from around 21 to 17 GHz. Exploiting these results, it may be feasible to inexpensively integrate transistors with better f _T-BV_CEO and f_T-V_A tradeoffs for analog and power handling characteristics along with transistors optimized for high-speed operation. These results also indicate that the buried island geometry control could be an issue for controlling electrical characteristics for scaled bipolar transistors     

Power performance of InP-based single and double heterojunctionbipolar transistors

The microwave and power performance of fabricated InP-based single and double heterojunction bipolar transistors (HBTs) is presented. The single heterojunction bipolar transistors (SHBTs), which had a 5000 Å InGaAs collector, had BV_CEO of 7.2 V and J_Cmax of 2×10⁵ A/cm². The resulting HBTs with 2×10 μm² emitters produced up to 1.1 mW/μm2 at 8 GHz with efficiencies over 30%. Double heterojunction bipolar transistors (DHBTs) with a 3000-Å InP collector had a BV_CEO of 9 V and J_{c max} of 1.1×10⁵ A/cm², resulting in power densities up to 1.9 mW/μm² at 8 GHz and a peak efficiency of 46%. Similar DHBTs with a 6000 Å InP collector had a higher BV_CEO of 18 V, but the J _{c max} decreased to 0.4×10⁵ A/cm² due to current blocking at the base-collector junction. Although the 6000 Å InP collector provided higher f_max and gain than the 3000 Å collector, the lower J_{c max} reduced its maximum power density below that of the SHBT wafer. The impact on power performance of various device characteristics, such as knee voltage, breakdown voltage, and maximum current density, are analyzed and discussed     

A 15-ns 32×32-b CMOS multiplier with an improved parallelstructure

A high-speed 32×32-b parallel multiplier with an improved parallel structure using 0.8-μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-×2.71-mm² die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved     

A high breakdown-voltage SiCN/Si heterojunction diode forhigh-temperature applications

Cubic crystalline p-SiCN films are deposited on n-Si(100) substrates to form SiCN/Si heterojunction diodes (HJDs) with a rapid thermal chemical vapor deposition (RTCVD) technique. The developed SiCN/Si HJDs exhibit good rectifying properties up to 200°C. At room temperature, the reverse breakdown voltage is more than 29 V at the leakage current density of 1.2×10^-4 A/cm². Even at 200°C, the typical breakdown voltage of SiCN/Si HJDs is still preserved about 5 V at the leakage current density of 1.47×10^-4 A/cm². These properties are better than the β-SiC on Si HJDs for high temperature applications