IEEE754标准浮点测试向量的生成

介绍了在IEEE754标准的规定下生成用于浮点功能部件的测试向量的方法，讨论了测试向量在数据通路上的差错覆盖率，并给出了对该方法的一些改进措施。     

VelociTI结构浮点DSPs寄存器堆读写的流水线设计

研究了VelociTI结构浮点数字信号处理器寄存器堆的流水线读写原理并提出了一种设计方法。该方法对单操作数双精度浮点指令采用2个32位数据通路用1个流水线周期读取源操作数，双操作数双精度浮点指令采用锁定译码单元，利用若干流水线周期读取源操作数。采用写控制向量的方法实现了流水线多个周期执行写操作。该方法正确实现了基于IEEE754标准的双精度浮点数据在寄存器堆与功能单元之间的32位数据通路上的传输，仿真结果验证了其正确性。     

基于FPGA的整数开方运算

在使用FPGA作为控制芯片对发电机进行控制时,发电机的三相电压有效值计算涉及到开方运算。若要在FPGA上实现某个数的开方运算,QuartusII提供了开方模块altfp_sqrt,但是这个模块有严格的使用要求,要求用户输入的被开方数是IEEE754标准浮点数,altfp_sqrt模块的输出结果也是IEEE754标准浮点数。这种浮点数不便于用户使用和阅读。用VHDL语言提出了一种基于FPGA的整数转换为IEEE754标准浮点数的方法,同时也提出了基于FPGA的IEEE754标准浮点数转化为整数的方法,应用这两种方法再结合Quartus II提供的altfp_sqrt模块实现了对整数的开方运算。以Quartus II为软件工具,以Cyclone II系列的EP2C8Q208C8为硬件平台,在发电机控制应用中对方法的正确性给予了证明。     

基于编译时插桩的浮点异常检测方法

浮点数是实数的有限精度编码,在进行浮点计算时,可能会导致不精确或者异常的结果,因此实现有效的浮点异常检测方法很重要。现有异常检测方法不面向浮点数学函数,由此提出了一种面向浮点数学函数的异常检测方法。该方法依据IEEE-754标准中定义的上溢出、下溢出、被零除、无效操作和不精确5类异常,并结合申威高性能数学函数库中使用的浮点控制寄存器FPCR和IEEE-754标准定义的浮点异常产生条件的相关理论,通过将异常类型和浮点运算指令进行对应分类,在程序编译时进行插桩以检测出浮点数学函数中出现的异常,同时记录代码覆盖率。最后将该方法应用于数学函数库,对库中100多个浮点数学函数进行了测试实验。实验结果表明,该浮点异常检测方法能够有效检测各类异常。     

The Interval-Enhanced GNU Fortran Compiler

Compiler support for intervals as intrinsic data types is essential for promoting the development and wide-spread use of interval software. It also plays an important role in encouraging the development of hardware support for interval arithmetic. This paper describes modifications made to the GNU Fortran Compiler to provide support for interval arithmetic. These modifications are based on a recently proposed Fortran 77 Interval Arithmetic Specification, which provides a standard for supporting interval arithmetic in Fortran. This paper also describes the design of the compiler's interval runtime libraries and the methodology used to test the compiler. The compiler and runtime libraries are designed to be portable to platforms that support the IEEE 754 floating point standard.     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.     

Floating point arithmetic teaching for computational science

Computational science is based upon numerical computing and, consequently, requires excellent knowledge of floating point computer arithmetic. In general, the average computational science student has a relatively limited understanding of the implications of floating point computation. This paper presents an initiative to teach floating point number representation and arithmetic in undergraduate courses in computational science. The approach is based on carefully designed practical exercises which highlight the main properties and computational issues of finite length number representation and arithmetic. In conjunction to the exercises, an auxiliary educational tool constitutes a valuable support for students to learn and understand the concepts involved. Simpler formats are used as an introduction to the IEEE 754 standard, with the aim of presenting the fundamentals of the floating point computation and emphasizing its limitations. This approach could be included in courses related to computer organization, programming, discrete mathematics, numerical methods or scientific computing in computational science curricula.     

Symbolic execution of floating‐point computations

Symbolic execution is a classical program testing technique which evaluates a selected control flow path with symbolic input data. A constraint solver can be used to enforce the satisfiability of the extracted path conditions as well as to derive test data. Whenever path conditions contain floating‐point computations, a common strategy consists of using a constraint solver over the rationals or the reals. Unfortunately, even in a fully IEEE‐754‐compliant environment, this leads not only to approximations but also can compromise correctness: a path can be labelled as infeasible although there exists floating‐point input data that satisfy it. In this paper, the peculiarities of symbolic execution of programs with floating‐point numbers are addressed. Issues in the symbolic execution of this kind of program are carefully examined and a constraint solver is described that supports constraints over floating‐point numbers. Preliminary experimental results demonstrate the value of the approach proposed. Copyright © 2005 John Wiley & Sons, Ltd.     

Evaluation of Standard Graphics Packages

In order to compare the quality of different implementations of GKS, the ISO0 standard for computer graphics, an evaluation method for GKS implementations is presented. It is based upon several groups of criteria. One group of criteria is concerned with performance, by which we understand here the memory requirements and time requirements for programs using GKS functions. A program that measures the performance of GKS packages is presented. Results of this evaluation method with several commercially available GKS implementations are described in summary. A checklist for evaluation of standard graphics packages is added as an appendix.     

嵌入式系统中48位高精度浮点类型的设计与实现

本文参考IEEE754标准,用无符号整型定义48位高精度浮点类型,详细给出了48位浮点类型与无符号32位整型相互转化及加减乘除的实现方法和流程图。算法已在ATMEL 89C55和PIC16F877中通过测试,并在基于SST9—三轴加速度传感器的控制处理中得到应用。     

计算机迭代下混沌序列的周期研究

研究了计算机迭代下基于浮点格式的混沌序列周期及其分布规律。通过构造与标准浮点格式匹配的非标准浮点格式,统计测算了六种常见混沌系统在不同浮点精度下退化的混沌序列周期及其分布,采用线性拟合方法获得了混沌序列周期随计算精度变化的分布关系,纠正了多年来基于定点格式的相应分布关系,为后续的混沌抗退化机制研究提供了一个合理的可用于实验测试的参考标准,也表明对于混沌序列而言,基于定点格式的结论不能简单随意推广到浮点格式。     

浮点开方运算单元的电路设计

文章提出了一种基于逐位循环开方算法,"四位一开方"的浮点开方运算单元的电路设计方案,使限制周期时间的循环迭代部分的门级数降低到14级。按14级门延时为周期时间计算,完成一个IEEE单、双精度浮点数的开方运算分别需要15和29周期。同时,文章对目前开方运算所采用的两类主要的算法-逐位循环开方算法和牛顿－莱福森迭代开方算法进行了描述,其中包括数的冗余表示等内容。     

Deriving Test Suites with the Guaranteed Fault Coverage for Extended Finite State Machines

Extended finite state machines (EFSMs) are widely used when deriving tests for checking the functional requirements for software implementations. However, the fault coverage of EFSMbased tests covering appropriate paths, variables, etc., remains rather obscure. Furthermore, these tests are known be incapable of detecting many functional faults frequently occurring in EFSM-based implementations. In this paper, an approach is proposed for deriving complete tests with the help of a proper Java EFSM implementation. Since the software is based on a template, the faults turn directly into EFSM faults. The method proposed here makes it possible to derive test suites that can detect functional faults. In the first step, the EFSM-based test suite derived by a well-known method is checked for completeness with respect to the faults generated by the μJava tool. Then, each undetected fault is easily mapped into an EFSM mutant. In the next step, some FSM abstraction is used to derive a distinguishing sequence for two finite-state machines (if such a sequence exists), which is added to the current test suite. The test derived in this way is complete with respect to the faults generated by μJava. If the corresponding FSM derived by EFSM modeling is too complex or no such FSM can be derived, the resulting test suite can be incomplete. However, the experiments performed by us clearly show that the original test suite extended by distinguishing sequences can detect many functional faults in software implementations when the given EFSM is used as a specification for the system.     

Floating Point Verification in HOL Light: The Exponential Function

Since they often embody compact but mathematically sophisticated algorithms, operations for computing the common transcendental functions in floating point arithmetic seem good targets for formal verification using a mechanical theorem prover. We discuss some of the general issues that arise in verifications of this class, and then present a machine-checked verification of an algorithm for computing the exponential function in IEEE-754 standard binary floating point arithmetic. We confirm (indeed strengthen) the main result of a previousl published error analysis, though we uncover a minor error in the hand proof and are forced to confront several subtle issues that might easily be overlooked informally.The development described here includes, apart from the proof itself, a formalization of IEEE arithmetic, a mathematical semantics for the programming language in which the algorithm is expressed, and the body of pure mathematics needed. All this is developed logically from first principles using the HOL Light prover, which guarantees strict adherence to simple rules of inference while allowing the user to perform proofs using higher-level derived rules.     

Formal Verification of the <Emphasis Type="Italic">VAMP</Emphasis> Floating Point Unit

We report on the formal verification of the floating point unit used in the VAMP processor. The dual-precision FPU is IEEE compliant and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions.We have formalized the IEEE standard 754. The formalization is supplemented by a rich theory of rounding, which includes notations and theorems facilitating the verification of the actual hardware. The theory of rounding enables the separation of the hardware into smaller modules which can be verified individually. Each module is verified on the gate level against a formal specification. The combination of these formal specifications, together with the theorems from the theory of rounding, yield the overall correctness of the FPU, i.e., theorems stating that the gate-level hardware complies with the high-level formalization of the IEEE standard. The verification is done completely in the theorem prover PVS.We further report on the implementation and test of the verified FPU on a Xilinx FPGA.     

Complete open-state testing of limitedly nondeterministic systems

An approach to the problem of complete testing is proposed. Testing is interpreted as the check of an implementation’s conformance to the given requirements described by a specification. The completeness means that a test suite finds all the possible implementation errors. In practice, testing must end in a finite amount of time. In the general case, the requirements of completeness and finiteness contradict each other. However, finite complete test suites can be constructed for certain classes of implementations and specifications provided that there are specific test capabilities. Test algorithms are proposed for finite specifications and finite implementations with limited nondeterminism for the case of open-state testing. The complexity of those algorithms is estimated.     

Differential evolution approach for optimal reactive power dispatch

Differential evolution based optimal reactive power dispatch for real power loss minimization in power system is presented in this paper. The proposed methodology determines control variable settings such as generator terminal voltages, tap positions and the number of shunts to be switched, for real power loss minimization in the transmission system. The problem is formulated as a mixed integer nonlinear optimization problem. A generic penalty function method, which does not require any penalty coefficient, is employed for constraint handling. The formulation also checks for the feasibility of the optimal control variable setting from a voltage security point of view by using a voltage collapse proximity indicator. The algorithm is tested on standard IEEE 14, IEEE 30, and IEEE 118-Bus test systems. To show the effectiveness of proposed method the results are compared with Particle Swarm Optimization and a conventional optimization technique – Sequential Quadratic Programming.     

高性能双精度浮点除法器研究

以IEEE 754标准为基础,完成了双精度浮点除法器的设计.整个设计包括预处理、指数减、尾数除、规格化、舍入判断、溢出判断和异常处理六部分.在尾数除部分用了SRT基4算法和改进的全并行基4、基8、基16和基256这5种不同的除法算法来实现.并分析了仿真和逻辑综合的结果,它们各自有不同的优点,可以适用不同的场合.如果综合考虑时钟周期数、时延、面积等方面的因素,全并行基8和基16算法是比较理想的选择.     

3D透视校正纹理映射矩阵电路设计及实现

3D图形硬件加速中,纹理映射属于像素处理阶段,透视校正中的纹理地址计算的特点是计算量大,且有实时性要求。本文设计了一个流水线脉动阵列结构来提高数据吞吐量。阵列的处理器单元(PE)为基于IEEE754单精度的32位浮点乘累加器,同时计算纹理坐标的除法电路也为单精度。     

FPGA Based High Performance Double-Precision Matrix Multiplication

We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from 1 to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for design-I. This compares favourably with both related art and general purpose CPU implementations.