一种用于IR-UWB收发器的4GHz正交输出小数频率综合器

本文针对工作于3.1GHz到5GHz频段的IR-UWB收发器,设计了一种4GHz小数频率综合器。该频率综合器采用0.18μm混合&射频CMOS工艺实现,其输出频率范围为3.74GHz到4.44GHz。通过使用多比特量化的∑-△调制器,该频率综合器在参考频率为20MHz时的输出频率分辨率达到15Hz。测试结果表明,该频率综合器的正交信号输出幅度失配和相位误差分别低于0.1dB和0.8º。该频率综合器的输出相位噪声达到-116dBc/Hz@3MHz,频谱杂散低于-60dBc。在1.8V电源电压下,该频率综合器的核心电路功耗仅为38.2mW。     

今日电子市场

日本电气公司(NEC)新近推出Versa E系列笔记本式计算机。E代表Enhanced,即增强型,性能优于原来的产品。 Versa E系列的基本特点是灵活可变,可根据需要选择120MB、209MB、250MB或340MB硬盘驱动,可以更新升级,随时提高工作效率。该机前侧装有一新式综合控制球,作     

串行输入PLL集成频率合成器MB15A02及其应用

MB15A02是日本富士通公司开发的集成PLL频率合成器。它采用变模分频技术。是一个单片串行输入PLL频率合成器。MB15A02具有如下特点：     

一种集成新型相位切换预分频器和高品质因素压控振荡器5 GHz CMOS频率综合器

本文实现了一种集成新型相位切换预分频器和高品质因素压控振荡器的锁相环频率综合器。该频率综合器在考虑噪声性能的基础上进行系统参数设计。预分频器采用了一种不易受工艺偏差影响的相位切换方式。对压控振荡器的电感开关电容和压控电容的品质因素进行了优化。与其他文献相比,该频率综合器使用相近的功耗取得更好的噪声性能。本文提出的频率综合器采用SMIC0.13微米工艺流片,芯片面积为11502500 μm²。当锁定在5 GHz时,其功耗在1.2V电源电压供电时为15mA。此时,1MHz频偏处相位噪声为-122.45dBc/Hz。     

Ku频段卫星通信微波频率综合器

本文介绍了一种用于卫星通信Ku频段微波频率综合器。首先讨论了该综合器方案设计考虑并对关键技术指标相位噪声进行了简要分析,着重介绍了频率综合器中主要部件的设计制作,最后给出了Ku频段微波频率综合器主要性能指标。     

一种改进的対拓Vivaldi天线设计（英文）

提出了一种新颖的対拓Vivaldi天线.该天线的辐射耀斑用新的复合指数曲线修正.为改善天线的辐射特性(增益,波束偏离和交叉极化),采用了一个新的引向器,该引向器由两个混合椭圆金属贴片构成.测试结果表明该天线在1~40 GHz频率范围内增益0 dBi,并且在15~40 GHz频段内天线的增益12 dBi.在3~40 GHz频率范围内,E面的波束偏离小于3°,并且在15~40 GHz不超过2°.     

双环路集成锁相频率合成器MB15U36的原理与应用

介绍日本富士通(Fujitsu)公司生产的MB15U36双环集成锁相环频率合成器的内部结构及原理，深入研究其结构特点，并在此基础上给出一个基于MB15U36的频率合成器设计方案。设计的环路滤波器可较好地满足工程设计中对相位噪声的要求．     

基于Simulink的∑△小数N频率综合器行为级仿真

快速有效的频率综合器系统级仿真可对∑△小数N频率综合器的设计实现提供有效的帮助.在分析小数N频率综合器的基础上,建立了完整的Simulink电路仿真模型,进行快速的准电路级行为仿真,可更好表现频率综合器的时域特性,验证电路结构的正确性.仿真结果表明该方法是简捷有效的.     

雷达频率综合器两种合成形式的探讨

本文从雷达频率综合器的主要性能要求出发,阐述了频率综合器的两种合成形式,并对它们的主要性能进行了比较;介绍了一种混合式雷达频率综合器方案,并给出了实验结果。     

毫米波频率综合器研究进展

频率综合器的性能对通信系统有极大的影响,本文简要介绍了频率综合器的基本原理,系统全面地综述了毫米波频率综合器的国内外研究进展,着重报道了单片微波集成电路(MMIC)工艺实现的60GHz锁相频率综合器理论和实验研究最新成果,分析了各种电路实现的优点和不足之处,预测了毫米波频综的发展趋势及相关技术要求,提出了一些有益建议。     

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

可键控高频频率合成器的设计

频率合成是将一个高稳定度和高精度的基准频率经过四则运算,产生同样稳定度和准确度的任意频率的技术。文中采用可编程数字频率合成芯片MC145151-2,结合单片机技术对频率步进值和输出频率值进行选择和控制,实现频率设置的程控化,完成输出频率在90 MHz~110 MHz范围变化的高频频率合成器的设计。阐述了该高频频率合成器软、硬件设计过程和参数计算方法,并对其进行各指标测试,结果表明该频率合成器具有较低的相位噪声、很高的频率稳定度。     

宽带低噪声CMOS数字电视频率综合器

介绍了一块CMOS数字电视调谐芯片中的宽带PLL频率综合器。该芯片使用经典的单变频三波段结构,VCO通过片外谐振回路产生了从80MHz到910MHz的频率用于电视调谐。VCO模块采用了独创的稳幅机制来满足输出的幅度和相噪特性在宽带范围内的基本一致;同时对电荷泵的电流失配和输出噪声之间的关系进行了分析,优化了电流失配,同时获得了较好的输出噪声。该频率综合器采用3.3V 0.35μm CMOS RF工艺,满足了DVB-CQAM64数字电视的低噪声要求,实现了清晰的数字电视接收,最后给出了测试结果。     

Spur-Suppression Techniques for Frequency Synthesizers

A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 mum CMOS technology. The chip area is 1.3 mm times 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 mus within 20 ppm of the target frequency.     

A 1-V 5.2-GHz CMOS synthesizer for WLAN applications

A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-/spl mu/m CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm/sup 2/.     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process     

全集成低噪声CMOS宽带分数分频频率综合器

设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².