The effect of fluorine on MOSFET channel length

The effect of fluorine on MOS device channel length has been evaluated. Fluorine has been introduced into the transistor by self-aligned ion implantation after the lightly doped drain (LDD) implant. The impact of fluorine in the LDD region, and its effect on the electrically determined channel length (L_eff), has been examined. Measurements taken from 0.6-μm LDD MOSFETs show a significant dependence of the L_eff on fluorine implant dose. The n⁺ resistor also shows more width reduction compared to unfluorinated samples. The decrease in channel length reduction by adding fluorine in the LDD region may yield way to relieve short-channel effects for the continuous scaling of CMOS devices into the deep-submicrometer region     

Power-supply voltage impact on circuit performance for half andlower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E_cL_eff, where E_c is the critical electric field necessary to cause carrier velocity saturation and L_eff is the effective channel length, is introduced. Experimental results confirmed that 1.1E_cL_eff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 μm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E_cL_eff can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-μm channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E_cL_eff     

A model for hot-electron-induced MOSFET linear-current degradationbased on mobility reduction due to interface-state generation

A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E_eff. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L_eff=0.2-1.5 μm and T_ox=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient α, which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E_eff determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L_eff and T _ox     

Scaling properties and short-channel effects in submicrometerAlGaAs/GaAs MODFET's: A Monte Carlo study

Scaling properties of n⁺-Al_xGa_1-xAs/GaAs MODFETs with submicrometer gate lengths (L_G=0.50 to 0.05 μm) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be ≈0.10 μm. Devices with smaller gate lengths than 0.1 μm exhibit degraded transconductance (g_m), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (R_o). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from g_m and f_t measurements are reconciled     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Silicon MOS transconductance scaling into the overshoot regime

Simulations incorporating velocity overshoot are used to derive the dependence of deep-submicrometer MOS transconductance on low-field mobility μ_eff and channel length L_ch. In contract to strict velocity saturation, saturated transconductance departs from a strict μ_eff/L_ch dependence when overshoot is considered. Constraints on μ_eff derived from conventional scaling laws together with strong μ _eff dependencies in these regimes indicate the importance of low-field inversion layer control and optimization. Transconductance in saturation is shown to approach a well-defined limit for very high μ _eff     

Submilliamp threshold InGaAs-GaAs strained layer quantum-well laser

Strained-layer InGaAs-GaAs single-quantum-well buried-heterostructure lasers were fabricated by a hybrid beam epitaxy and liquid-phase epitaxy technique. Very low threshold currents, 2.4 mA for an uncoated laser (L=425 μm) and 0.75 mA for a coated laser (R~0.9, L=198 μm), were obtained. A 3-dB modulation bandwidth of 7.6 GHz was demonstrated at low bias current (14 mA). Procedures for material preparation and device fabrication are introduced     

High-performance submicrometer undergated thin-film transistorswithout high-temperature rapid thermal annealing or plasma hydrogenation

High-performance submicrometer undergated thin-film transistors (TFTs) are fabricated without using high-temperature rapid thermal annealing or plasma hydrogenation. These processes are used in the state-of-the-art devices, but avoided in current manufacturing. For a 0.35-μm×0.35-μm device and a 0.7-μm×0.5-μm device, I_ON of 3 and 1.2 μA are obtained with ON/OFF current ratios of 4×10⁵ and 1.2×10⁸ , respectively, very close to that of state-of-the-art devices. A new lightly-doped-drain (LDD) structure is employed to improve I_ON reproducibility, which is difficult to achieve for deep-submicrometer devices with the conventional lightly-doped-offset (LDO) structure     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

Delay time analysis for 0.4- to 5-μm-gate InAlAs-InGaAs HEMTs

InAlAs-InGaAs HEMTs with 0.4- to 5-μm gate lengths have been fabricated and a maximum f_T of 84 GHz has been obtained by a device with a 0.4-μm gate length. A simple analysis of their delay times was performed. It was found that gradual channel approximation with a field-dependent mobility model with E_c of 5 kV/cm holds for long-channel devices (L _g>2 μm), while a saturated velocity model with a saturated velocity of 2.7×10⁷ cm/s holds for short-channel devices (L_g<1 μm)     

Capacitance allocation and its role in the performance ofdoubling-circuit pulsed gas lasers: its application to the N2laser

An investigation of the optical output for all possible combinations between the capacitances, C₁ and C ₂, in a doubling circuit N₂ laser is presented. It is shown that a maximum optical output appears when C ₁=C₂ for constant total capacitance. The maximum value increases when the total capacitance increases and the system approaches saturation for capacitance values higher than 20 nF each. This behavior of the optical energy is due to a similar behavior of the current, which becomes maximum when the best coupling of the two loops of the system is achieved through capacitance equality, and the oscillatory behavior of the system is minimized. When this equality is disturbed, either with weak (C₁>C₂ ) or strong (C₂<C₁) coupling of the system, the current and optical outputs decrease. In both cases, the undesirable oscillatory behavior of the system increases. The electric parameters R₁,L₁ of the spark-gap loop and R₂,L₂ of the laser channel loop are calculated     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

Mobility profiles in short and narrow GaAs MESFET channels

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN_x-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L_G =10, 4, 2, 1, 0.8, 0.5, 0.3 μm, W_G=20 μm; W_G-100, 40, 20, 10, 4, 2 μm, L _G=0.5 μm). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN _x-gate fabrication process. Injected excess charges at gate length below 0.5 μm distorts the mobility evaluations     

A recessed-gate InAlAs/n+-InP HFET with an InP etch-stoplayer

The authors have exploited both the attractive transport properties and the etch selectivity of InP in a novel InAlAs/n⁺ -InP metal-insulator-doped-channel heterostructure FET (MIDFET). In several other material systems, the MIDFET has been shown to be well-suited to high-power telecommunications applications. The device employs InP both as the channel layer and as an etch-stop layer in a selective-etch recessed-gate process. L_g=1.8-μm devices achieve g_m and I_D,max values of 224 mS/mm and 408 mA/mm, respectively, the highest recorded values for an InP channel HFET with L_g⩾0.8-μm, including MODFETs. These figures combine with a breakdown voltage of 10 V and peak values of f _T and f_max of 10.5 and 28 GHz, respectively. The selective-etch recessed-gate process contributes to excellent device performance while maintaining a tight 60-mV threshold voltage distribution (13 mV between adjacent devices)     

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 μm L_eff, self-aligned TiSi₂ double-level metal, and an average minimum feature size of 1.35 μm. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed