Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A. Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in VLSI Architecture and is also thesis director. His main research interests are integrated circuit architecture, embedded systems, signal processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.     

Statistical Tolerance Analysis for Assured Analog Test Coverage

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.     

An Analog Checker with Input-Relative Tolerance for Duplicate Signals

We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. The key feature of the proposed checker is that it establishes a test criterion that is dynamically adapted to the magnitude of its input signals, thus enhancing the accuracy of assessing their relative discrepancy. Consequently, when this checker is utilized in concurrent error detection, it diminishes the probability of both false negatives and false positives. Likewise, when employed for off-line test purposes, the checker supports both high yield and high fault coverage. In contrast, checkers implementing a static test criterion may only be tuned to achieve efficiently one of the aforementioned objectives.     

模拟电路的振荡测试技术

集成电路设计和制造技术的发展给电路测试带来了巨大的挑战,其中模拟电路的测试是电路测试的难点.目前在这一领域有许多致力于降低测试难度,节约测试成本的研究.介绍了一种称为"振荡测试"的模拟电路测试技术,从振荡电路的构造、测试响应的测量和分析等方面综述了振荡测试技术的研究现状,同时总结了振荡测试技术的优点,分析了当前存在的局限性,并对将来的发展进行了展望.     

A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters

This paper presents a strategy for synthesizing analog cascaded filters with optimal test point insertion. The strategy is based on the implementation of a selective divide-and-conquer approach that permits to ensure high fault detection capabilities while limiting DFT penalties and reducing test time. The proposed solution relies on the evaluation of the filter testability at the different inputs and outputs of the cascaded blocks in order to add DFT only when this testability is not sufficient. Efficient testability evaluation is provided through high-level fault modeling and simulation.This revised version was published online in March 2005 with corrections to the first authors name and the cover date.     

新型程控模拟量发生器

对 SIMI2 0 0 0数模 IC测试系统的模拟量发生器进行了改进 ,采用多级分布式流水线步进传输结构 ,解决了从控制器到终端之间的数据传输问题以及灵活扩展的问题     

Fault Simulation for Analog Circuits Under Parameter Variations

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

一种对测试频率不敏感的模拟电路多频参数识别方法

在模拟电路的多频参数识别方法中，一般都存在诊断方程的解对测试频率敏感的问题。针对文献中的多频参数识别方法，提出了2种克服诊断方程对测试频率敏感的技术。并对提出的方法进行了电路仿真验证。     

一种可应用于并发在线测试的扫描单元设计

航天等领域对集成电路可靠性要求较高,要求其具有在线测试功能,以便及时发现故障,减少损失。结合现有扫描设计方法,设计了一种改进的扫描单元结构。将该扫描单元应用于时序电路后,能够在电路工作的同时进行测试;通过灵活的时钟选择机制,方便地控制电路进行非并发和并发测试。仿真实验表明,应用本文提出的扫描单元,时序电路能够在增加一定硬件冗余的条件下实现在线测试,时间开销较小,有较高的可靠性和一定的容错能力,实用性强。     

模拟电路故障诊断的结点电压灵敏度比值法

在证明线性电路中结点电压变化量比值等于结点电压灵敏度比值的基础上,提出了结点电压灵敏度比值法,通过结点电压变化量比值和结点电压灵敏度比值的比对确定电路的故障元件。理论分析和实验结果表明,该方法算法简单、诊断速度快,在可测点受限条件下具有较高的诊断精度,特别适合大规模线性模拟电路的故障诊断和测试。     

An Analog Circuit Fault Characterization Methodology

A methodology for diagnosing and characterizing multiple faults in analog circuits, and results from applying this methodology to a real circuit is presented. Our method is a novel combination of a Simulation Before Test (SBT) and Interpolation After Test (IAT) methodology. Our method uses the classical SBT concept of a fault dictionary database constructed before test. It also uses a method of IAT that consists in using the measurements to guide an interpolation algorithm to effectively increase the local resolution of the fault dictionary database and thereby yield the most likely test parameter value. Our methods underlying principle is to characterize the fault-free and faulty circuit cases by their impulse responses obtained by simulation and subsequently stored in a fault dictionary database. The method uses the technique of Lagrange interpolation to resolve the faults between the fault dictionary database entries and the actual measurements. Our experimental results reveal that the method is effective for characterizing faults when the simulations match the measurements sufficiently. Consequently, the methods effectiveness depends highly on the quality of the models used to build the dictionary as well as on the accuracy of the measurements.Yvan Maidon was born in Bordeaux, France. He received the M.Sc degree in (electronics) applied physics from the University of Bordeaux, in 1980. He is currently Head of the Department for Applied Sciences in Electrical and Electronic Engineering at the University of Bordeaux 1. His special research interests include failure analysis and relaibility of analog circuits. He has also developed original BICS for mixed circuits and SoC testing.Thomas Zimmer is currently Professor at the University of Bordeaux 1. He received the M.Sc. degree in physics from the University of Würzburg, Germany, in 1989 and the Ph.D. degree in electronics from the University of Bordeaux 1, France, in 1992. His research interests include characterization and modeling of high frequency bipolar devices. He has authored and co-authored about 70 scientific and technical publications including several book chapters. He is also co-founder of the start-up company XMOD.André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS 02) and the General Chair for VTS 03 and VTS 04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwers Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Societys Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia.     

A New Optimal Test Node Selection Method for Analog Circuit

The existing test node selection methods of analog dictionary technique assume that the voltage gap of ambiguity group is 0.7?V. However, this technique is not always accurate to determine the right ambiguity gap for each fault mode. As the probability density of the circuit output approximately satisfies the normal distribution, an accurate technique is introduced to determine the ambiguity gap. Then, this paper proposes a new test node selection method with an extended fault dictionary and the overlapped area values. Firstly, the fault dictionary is constructed with the mean and standard variance values of node voltage. Then, the area detection table is generated by the overlapped area values under normal curves for ambiguity faults, which represent the failure probability of ambiguity faults. Finally, the optimal test node set is selected by fusing fault isolation and overlapped area information. The results show that the proposed method is effective to select the optimal test node set and improve the performance of analog fault diagnosis.     

一种模拟滤波电路数字化方法

在信号处理中,滤波的优劣直接影响信息的准确性。模拟滤波虽然快捷但不灵活,数字滤波效果虽好但复杂。所以文中提出一种以模拟滤波器为基准,设计具有相同功能而且参数可调的数字滤波器的方法。并以二阶RC无源低通滤波电路为例对此过程进行说明,与模拟滤波电路和传统的数字滤波相比,该方法不仅比传统的数字滤波算法简单快捷,而且可有效防止模拟电路中器件的寄生参数、精度、温度等的影响,使滤波更加稳定。     

模拟集成电路参数型故障定位方法

针对模拟集成电路参数型故障的测试难题,提出了定位模拟集成电路参数型故障的功率谱相关分析方法.利用小波滤波器组对被测电路响应进行子带滤波后,计算子带响应序列的相干函数.通过对以相干函数序列表征的功率谱进行相关分析,不仅可以实现模拟集成电路参数型故障的数字化故障特征提取,而且还可以完成对参数型故障的定位.利用国际标准电路ITC97的状态变量滤波器和跳蛙滤波器,通过对比实验,验证了本文方法对定位参数型故障的有效性,为实现模拟集成电路参数型故障诊断的高覆盖率和诊断自动化提供了一种新途径.     

一种新型的基于DSP的全数字在线式UPS

介绍了一种新型的基于TMS320LF2407控制芯片的全数字在线式不间断电源,并分析了该UPS的工作原理,实验结果表明该电源具有结构简单,控制方便,抗干扰能力强等优点。     

模拟集成电路参数型故障定位方法

针对模拟集成电路参数型故障的测试难题,提出了定位模拟集成电路参数型故障的功率谱相关分析方法.利用小波滤波器组对被测电路响应进行子带滤波后,计算子带响应序列的相干函数.通过对以相干函数序列表征的功率谱进行相关分析,不仅可以实现模拟集成电路参数型故障的数字化故障特征提取,而且还可以完成对参数型故障的定位.利用国际标准电路ITC97的状态变量滤波器和跳蛙滤波器,通过对比实验,验证了本文方法对定位参数型故障的有效性,为实现模拟集成电路参数型故障诊断的高覆盖率和诊断自动化提供了一种新途径.     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.