数字温度传感器中低功耗数字滤波器设计

设计了一种应用于数字温度传感器的低功耗CIC(Cascade-Integrated-Comb)抽取滤波器。在功能上,控制滤波器单次转换和抽取倍数可变;在架构上,采用非递归和多相分解的方式分六级实现CIC滤波器。通过利用不同相位的时钟控制多相分解的各个通道数据传输,避免产生多相分解控制逻辑电路。采用同步和异步分频相结合的技术产生时钟分频电路,减少分频电路的复杂性。使用资源共享技术及将乘法运算转换为移位相加运算,能够减少多相分解引入的系数对电路的影响。经过逻辑综合和功耗分析验证表明:设计的滤波器系统功耗为流水线Hogenauer CIC系统功耗的28.6%,为传统非递归CIC滤波器系统功耗的45%。     

一种基于多相带通结构的信道化滤波器算法

针对信道化滤波器要求运算速度快、消耗资源多、难以实时处理的突出问题，从多相滤波器，信道化滤波器的结构、原理和运算效率分析出发，推导了一种基于多相带通结构的信道化滤波器算法模型。这种算法将现有多相结构信道化滤波器模型中的低通设计改为带通设计，实现了复数乘法运算全部集中在带通滤波环节当中，并采用协调分级DFT算法的实现方案，大幅度节省了硬件资源，提高了运算效率，实现了信道化滤波器在通用FP—GA和DSP芯片中的实时处理，硬件仿真结果验证了算法模型的正确性和有效性。     

基于多相带通滤波的变带宽数字下变频器设计

为了使数字下变频器适应多种带宽信号的处理能力,在研究数字下变频和多相结构运算特点的基础上,提出一种多相带通滤波结构.首先通过将下变频运算等效为带通滤波有效降低了运算量,分析得出一定条件下,采用适量乘法器就能完成各种抽取比下的乘法运算的结论,并以此对多相结构进行改进,得到带通滤波的多相通用结构;然后利用恒速乘法、多速率输入输出技术巧妙实现变带宽滤波.文中还对不同带宽下的滤波器系数和性能进行了分析.软硬件仿真表明,该结构不仅能够实现多种带宽信号的数字下变频,而且具有低复杂度、较高的运算效率和较少的硬件开销.     

整数提升小波多相矩阵分解系数的快速提取算法

整数提升小波多相矩阵分解系数不唯一,选取方法多样,计算量大。首先采用滤波器迭代次数选取算法,按照输入的信噪比(SNR)比例求出优化迭代次数;然后以非线性迭代比较算法为判定准则,结合求出的优化迭代次数,得到满足参数要求的优化分解系数。迭代次数是依据待测数据求得的,因此优化分解系数对该数据取得较好的处理效果,满足多相矩阵分解系数选取的要求。迭代比较算法满足收敛特性,通过比较滤波器的冲击和阶跃响应是否满足设定的误差限,可减少迭代运算次数,快速准确地选取优化小波系数。通过实验分析可知,该快速提取算法能有效满足数据处理的要求,减少待测数据处理的计算量,提高数据处理的效率。     

FIR滤波器的高速实现

介绍了一种实现FIR滤波器高速运算的有效方法。该方法在传统的滤波嚣系数奇偶对称性的基础上，根据系数经System View软件量化后成比例的特点，利用加法运算采简化卷积中大量繁琐耗时的乘法运算；同时推导出奇偶对称性的运算规律并给出详细运算步骤和计算公式。最后给出该算法分别与仅利用系数对称性、直接卷积两方法相比较的加速比。仿真结果表明，文中所采取的优化措施能够提高信号处理速度。     

高精度∑-△ DAC中插值滤波器的研究与设计

基于系统研究插值滤波器理论,选用了两级半带滤波器实现4×插值和级联32×采样保持电路,设计了一种适用于高精度音频过采样∑-△DAC的128×数字内插滤波器.使用多相分解原理在系统级优化电路结构,并运用CSD编码,使得滤波器中的乘法运算仅需要移位实现,进一步节省了硬件面积.结果表明,在系数截短至16位字长以后,总的通带波纹不超过0.008dB,镜像频带衰减大于66dB.     

分数倍抽样率转换器的时变网络结构及其FPGA实现

提出了分数倍抽样率转换器的高效时变网络结构的设计方法,并用现场可编程门阵列（FPGA）实现.通过对分数倍抽样率转换器的多相结构与时变网络结构的比较,指出在实现分数倍抽样率转换器时,时变网络结构克服了分数延迟的问题,结构简单;整个设计采用并行工作方式以提高系统的运算速度;采用低抽样率下进行滤波运算,从而大大降低了运算量.以I/D=256/1 023倍抽样率转换器为例,用FPGA XC2V250-5来实现时变网络结构的设计,芯片利用率为61%,最高工作频率可达92.225 MHz.     

基于多项式变换的二维整型离散余弦变换快速算法

提出了一种基于多项式变换的二维整型离散余弦变换（DCT）快速算法,利用多项式变换将二维DCT变换的计算转化为一系列一维DCT变换及其变换系数的求和运算,减少了乘法和加法的计算量;利用提升矩阵,实现了整型DCT变换,进一步提高了运算效率的同时,使信号可精确重构。     

一种高效率的RSA模幂算法的研究

RSA硬件的执行效率主要取决于模幂运算的实现效率。该文旨在介绍一种引入中国剩余定理加速私钥操作,并采用Barret模缩减方法,避开除法运算,将模幂运算转换成三个乘法运算和一个加法运算的快速模幂算法及其硬件实现方法。在乘法运算的实现中,采用Booth乘法器,可以大大缩短电路的关键路径,显著地提高硬件的执行效率。     

参数化的Deslauriers-Dubuc插值小波——构造及图像编码性能分析

研究了采用提升构造具有任意偶数阶消失矩, 满足对称性, 且仅用一个自由参数表达的 Deslauriers-Dubuc (D-D)双正交插值小波. 首先,采用多相矩阵理论推导出了此类小波存在的条件; 然后,给出了对应小波滤波器和插值小波变换的构造算法. 采用算法具体构造了分别具有消失矩对(4, 2)、(4, 4)、(6, 2)以及(6, 4) 等4类一参数表达的D-D插值小波; 最后, 以自由参数为自变量, 根据编码增益准则, 优化设计了4种用于图像编码的插值小波, 其滤波器系数全为二进制分数, 可实现非乘法运算的离散小波变换(Discrete wavelet transform, DWT). 系统分析表明, 两种小波的压缩性能超过CDF-9/7小波, 对于纹理图像, PSNR增益达到0.44.dB, 并且计算复杂度可降低17%以上. 实验同时表明, 新小波的重构图像具有更好的主观可视质量.     

一种基于多相分解的分数抽样率变换研究

在频域上分析分数倍抽样率转换信号处理过程,为适用于实时系统,对其实现结构进行优化,给出一种高效的分数倍抽样率变换器多相结构优化实现方法,并将其应用于一维信号抽样率变换。仿真结果表明,抽样输出的一维序列信号与实际理想信号误差较小,所设计的分数抽样率变换器是有效可行的。     

Transformation to implement computationally efficient IIR decimation filters

A new technique is proposed to transform an IIR filter into a computationally efficient decimation filter. In this technique, the recursive transfer function is transformed and noble identity is invoked to get sample rate reduction. The magnitude and phase response of the original filter are unaltered after the transformation. A higher order IIR transfer function is decomposed into parallel first-order sections and each section is transformed for sample rate reduction. The transformation is computationally efficient since current output can be directly computed from single Mth old output and M inputs processed using polyphase decomposition. Filtering and down sampling are performed in the same stage. Filters are designed and mapped on FPGA. Hardware and computational complexities are reduced and throughput is enhanced.     

Theory and design of two-dimensional DFT modulated filter bank with arbitrary modulation and decimation matrices

It is well known that two-dimensional (2D) filter bank is far removed from a straightforward extension of one-dimensional (1D) filter bank. There are many challenging problems on the theory and design methods for the 2D filter bank. Among these problems, the perfect-reconstruction (PR) theory of the 2D DFT modulated filter bank with arbitrary modulation and decimation matrices remains an unsolved difficulty, which is the focus of this paper. The necessary and sufficient condition for perfect reconstruction (PR) is derived by using the polyphase decomposition of the analysis and synthesis filters, as well as the fast implementation structure of the filter bank. Then, the PR condition in frequency domain is transformed into a set of quadratic equations with respect to the prototype filter (PF), which is utilized to formulate the design problem into an unconstrained optimization problem. An efficient iterative algorithm is proposed to solve the problem. Numerical examples are included to verify the validity of the PR condition and the effectiveness of the design method.     

数字信道化高效结构设计及FPGA实现

针对宽带接收机中处理多个同时到达信号时的逻辑资源消耗大、实时性差、配置不灵活等问题，从多相滤波和采样率等价交换原理出发，对接收机前端信道化过程开展研究。提出了包含移位抽取模块、多相滤波模块和全并行快速傅里叶变换(FFT)模块的数字信道化高效实现结构；利用基于现场可编程门阵列(FPGA)的硬件描述语言实现了该高效结构。最后，给出了仿真验证和在线测试的结果，验证了该高效结构实现方式合理。在满足宽带接收机处理多个同步到达信号的同时，有效提高了处理速率，降低了资源消耗，为后续基带信号处理预留了更多的硬件资源。     

Taylor series expansion based repetitive controllers for power converters,subject to fractional delays

Digital repetitive controllers are widely employed to track/reject the periodic signals with zero steady-state error. Their implementation involves the use of single or multiple digital delay elements. Practically, the delay element is implemented by the use of memory locations, where samples are held and released after a specific number of sampling periods, equivalent to the desired time delay. A problem arises when the desired time delay becomes a non-integer multiple of the sampling time. Such time delays can be accurately realized by employing a fractional delay filterThis paper presents a Taylor Series expansion based digital repetitive controller designed to implement any (integer, non-integer) delay in the control of power converters, occurring due to uncontrollable variations in the reference frequency. The T3644aylor Series expansion transforms the fractional delay filter design problem to a differentiator/sub-filter design. Finite impulse response (FIR) and infinite impulse response (IIR) fractional delay (FD) filter concepts can be applied to realize the required fractional delay. This structure provides efficient on-line tuning capabilities i.e. FD can easily generate any required fractional delay without redesigning the filter when the delay parameter varies. An example is demonstrated to show the effectiveness of this approach, for a single-phase power inverter feeding a passive load.     

A Recursive Digital Filter Implementation for Noisy and Blurred Images

This paper presents the design and the implementation of an optimized Canny-Deriche edge detector. After a brief reminder of the filter's equations, we define different techniques to speed up the sampling rate of the IIR filter. In particular, improving the throughput rate of the IIR filter, we present a look-ahead with decomposition technique. This method leads us to design a first chip, which performs at a sampling rate of over 20 MHz with a silicon area of 60 mm². Using a local register retiming method, we have designed a second circuit, which is able to process a pixel in 30 ns with a silicon area of 30 mm². These two approaches are compared. This work leads us to an ASIC which was designed in a CMOS 1 μm technology and successfully tested.     

Optimum filter design for quantized multidimensional subband filter bank

This paper provides a rigorous theory for analysis of quantization effects and optimum filter bank design in quantized multidimensional subband filter banks. Each pdf-optimized quantizer is modeled by a nonlinear gain-plus-additive uncorrelated noise and embedded into the subband structure. Using polyphase decomposition of the analysis/synthesis filter banks, we derive the exact expression for the output mean square quantization error. Based on the minimization of the output mean square error, the technique for optimal filter design methodology is developed. Numerical design examples for optimum nonseparable paraunitary and biorthogonal filter banks are presented with a quincunx subsampling lattice.     

基于分布式算法的高阶FIR滤波器及其FPGA实现

提出一种新的高阶FIR滤波器的FPGA实现方法。该方法运用多相分解结构对高阶FIR滤波器进行降阶处理,采用改进的分布式算法来实现降阶后的FIR滤波器。设计了一系列阶数从8到1 024的FIR滤波器,通过Quartus II 7.1的综合与仿真,以及在EP2S60F1020C4 FPGA目标器件上的实现结果表明,该方法能够有效地减少硬件资源的使用且满足高速实时性的要求。