IEEE1149.4模拟和混合信号测试总线标准

模拟和混合信号边界扫描标准(IEEE1149.4)是针对电路板级外部分立元件的测试而发展起来的,该标准与IEEE1149.1兼容,另外,在此基础上,IEEE1149.4又增加了两根线,用来控制模拟信号.目前1149.4的标准,不但应用在传统的电路板上,在混合信号集成电路甚至包含混合信号的SoC系统芯片上,都有应用.本文...     

基于IEEE1149.4标准的验证电路设计

介绍了基于IEEE1149.4混合信号测试总线标准的验证电路设计,利用复杂可编程逻辑器件(CPLD)、模拟开关ADG202A和电压比较器LM3¨等器件,实现了该标准所定义的测试结构.它的设计与可观性实验及可控性实验验证了标准的有效性,对于今后推广标准在混合信号芯片中的应用将起到积极的作用.     

利用IEEE1149.1和1149.4进行模拟测试

所面临的挑战是发展一种从响应不可预测的混合信号器件的模拟部分获取数据的方法     

基于IEEE1149.4的测试方法研究

根据混合信号边界扫描测试的工作机制，提出了符合l149．4标准的测试方法，并用本研究室开发的混合信号边界扫描测试系统进行了测试验证。     

混合信号总线测试实例

混合信号电路(Mixed-signalCircuits)广泛应用于通信、多媒体、工业电子和消费类电子产品中。其测试方法有很多,其中基于边界扫描技术的混合信号测试总线已越来越受欢迎。在定义混合信号测试总线时,要求不仅能够测试桥接故障、开路故障、对模拟元件值进行测试,而且还要能够与IEEE1149.1兼容。为此,IEEE半导体工业协会(SA)标准委员会于1999年6月批准了建立混合信号测试总线标准的1149.4文件。     

一种混合信号边界扫描测试系统的设计

IEEE 1149.4的推出为混合信号测试提供了一个标准,推动了混合信号边界扫描测试技术的研究。简要介绍了IEEE 1149.4标准及混合信号测试方法,并根据标准定义的测试结构设计出一种混合信号边界扫描测试系统。经过测试验证,该系统能够对混合信号电路进行互连测试和参数测试,可实现准确的故障诊断,具有一定的实用价值。     

基于IEEE 1149.X标准的测试技术研究

IEEE1149标准及其子标准是基于边界扫描的测试技术，它们针对不同的应用环境采用相应的技术标准。它们所提供的解决方案极大地方便了芯片级、板级、系统级及数字网络的测试。本文讨论了IEEE1149．X中各标准的原理、结构，分析了各项技术的发展及应用，并举例说明了在实际中的测试应用。     

IEEE1149.1产生新标准

研制边界扫描原先是为了检验IC引线与PCB连接轨迹，现在它已被用于支持芯片调试、设备流程，混合信号测试和现场服务。     

集成电路测试相关标准研究与探讨

重点研究了纯数字信号、混合信号和片上系统测试的一些问题及相关标准，阐述了各标准的作用，分析了这些标准在实际应用中存在的一些问题及其局限性。     

边界扫描测试技术及可测性标准IEEE1149.1

这是一篇关于可与数字专用集成电路(ASIC)的设计结合在一起的边界扫描测试技术概念的综合性文章。本文包括了IEEE可测性标准1149.1——可在设计、开发数字ASIC及系统的过程中实行的边界扫描测试技术——的特性及讨论。这些测试技术可以用于测试系统中的数字ASIC器件、装有器件的多层印刷电路板(PCB)及多芯片模块(MCM)。     

An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1

ANSI/IEEE Std 1149.1 defines a standard implementation of boundary scan that, it is hoped, will be built into many catalog and application-specific integrated circuits. The standard was developed as a solution to two continuing trends that are having a significant, adverse, impact on the task of testing loaded printed wiring boards: increasing chip complexity and greater miniaturization. The former increases the difficulty of test generation, while the latter impedes access for the bed-of-nails and hand-held probes on which many established test techniques depend.This tutorial provides a guide to the principal features defined by the standard and to their operation. It is intended as a prelude to the standard itself, not as a substitute for it. In particular, it is recommended that readers who intend to implement integrated circuits, design tools, or test systems that support the standard read the standard document before doing so.     

Component Value Calculations and Characterizations for Measurements in the IEEE 1149.4 Environment

This paper describes a measurement principle for calculating component values from measurements conducted under less than optimal conditions, as is the case in the IEEE Std 1149.4 environment. Also presented are equations that take into account switch resistances on the signal paths, the output resistance of the signal generator, and the loading effect caused by the input impedance of the voltmeter together with the pin capacitances in parallel to the voltmeter. In addition, the paper presents characterization methods to determine values for these impedances. The inaccuracies achieved in the impedance range from kΩ to MΩ are of the order of few percent.

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.