一种用于信息处理微系统DDR互连故障的自测试算法

为解决信息处理微系统中双倍速率同步动态随机存储器（Double Data Rate, DDR）复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备（Auto Test Equipment,ATE）测试算法与板级系统的系统级测试（System Level Test, SLT）模式相结合,提出面向DDR类存储器的测试算法和实现技术途径。并基于现场可编程门阵列（Field Programmable Gate Array, FPGA）器件实现微系统内DDR互连故障的自测试,完成了典型算法的仿真模拟和实物测试验证。相较于使用ATE测试机台的存储器测试或通过用户层测试软件的测试方案,本文所采用的FPGA嵌入特定自测试算法方案可以实现典型DDR互连故障的高效覆盖,测试效率和测试成本均得到明显改善。     

基于边界扫描的板级互连测试模型研究

主要研究边界扫描技术在电路板互连测试中的应用,对互连测试的故障模型和测试方法进行优化.根据电路板制造故障的具体成因和分布情况,对基于边界扫描的板级互连测试模型进行扩展.提出以元器件焊点故障作为基本参考点,增加了网络两端发生不同故障的情况,从而总结出新的故障模型,并给出了针对新故障模型的测试方案.基于新的故障模型的测试可以更加全面地发现电路板的潜在问题,避免在生产测试中因为故障的漏判而反复维修,从而提高生产的效率.     

混合信号电子产品的自动测试技术

电子产品微型化使自动测试成为必然,而边界扫描技术则使自动测试成为可能。文章分析了1149.4和1149.1标准的测试访问端口,以及测试逻辑结构和测试协议的异同,提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型;在此基础上,详细阐述了两个标准在混合信号电子产品自动测试中的综合应用方法;最后,以典型的混合信号电路D/A转换器为例,对两个标准的综合应用进行了仿真验证。     

AS1747：低压模拟信号开关

奥地利微电子公司发布一款双SPDT（单刀／双掷）、低压模拟信号开关AS1747,扩展了其模拟开关系列。该开关是系列开关中首款具有负信号处理能力的器件,可实现无需AC耦合电容的音频应用设计。     

混合信号总线测试

文中介绍了使用本研究室开发的混合信号边界扫描测试系统对KLIC实验芯片进行简单互连、扩展互连测试和CLUSTER测试。通过对测试结果的分析表明，IEEE1149．4测试总线在这些测试中是非常成功的，并同时指出了其局限性。     

奥地利微电子新款模拟开关AS1747提升音频品质

奥地利微电子公司发布一款双SPDT（单刀／双掷）、低压模拟信号开关AS1747，扩展了其模拟开关系列。该开关是系列开关中首款具有负信号处理能力的器件，可实现无需AC耦合电容的音频应用设计。     

混合信号总线测试实验

使用本院CAT研究室开发的混合信号边界扫描测试系统对KLIC实验芯片进行简单互连、扩展互连测试和CLUSTER测试。通过对测试结果的分析表明，IEEE1149.4测试总线在这些测试中是非常成功的，同时指出其局限性。     

带GaAs TTL电平驱动器的SPDT开关的模拟和性能

介绍了一种带ＧａＡｓＴＴＬ电平驱动器及单刀双掷（ＳＰＤＴ）开关的设计、模拟和测试结果。驱动器的设计采用了开关输入稳压负载,建立了所用器件的大信号模型,对电路进行了模拟分析和优化,模拟和测试结果吻合较好,开关时间达到５ｎｓ,插入损耗小于１．０ｄＢ,隔离度大于６０ｄＢ。     

一种双模式的CMOS现场可编程模拟阵列的分析与设计

本篇文章提出了基于采用高度灵活的互连盒的互连网络的一种新型的现场可编程模拟阵列(FPAA)结构,该结构可以在双模式下工作包括离散时间模式和连续时间模式,以追求在不同应用场合下的性能要求。高度灵活的互连盒中的开关不仅用来作为可编程开关还直接作为开关电容中电荷转移的开关来使用,大大减少了离散时间模式下信号路径上的开关,提高了整体电路的性能。该款FPAA采用0.18um CMOS工艺,3.3V电源电压。后仿结果显示互连网络的最大带宽可达265MHz, 从示例的测试结果可以看出该款FPAA在连续时间模式下可工作在2MHz信号带宽下,无杂散动态范围可达54dB, 离散时间工作模式下的处理精度可达96.4%。     

边界扫描在带DSP芯片数字电路板测试中的应用

为了解决带DSP（数字信号处理器）芯片数字电路板中部分非边界扫描器件的功能测试难题,采用了边界扫描测试技术与传统的外部输入矢量测试相结合的方法,对一块带有DSP芯片数字电路板中的非边界扫描器件进行了功能测试。测试结果表明,该测试方法能够对这部分器件进行有效的故障检测和故障隔离,并可将故障隔离到芯片。充分说明这种应用边界扫描技术与传统测试方法相结合的功能测试方法能够有效地解决带DSP芯片数字电路板中部分非边界扫描器件的功能测试问题。     

混合信号边界扫描测试系统的设计与实现

分析了混合信号边界扫描测试的工作机制对测试系统的功能需求,实现了符合IEEE1149.4标准的混合信号边界扫描测试系统。仿真和测试实践表明,该测试系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,结构简单、携带方便、工作可靠。     

Block-oriented programmable design with switching networkinterconnect

A block-oriented programmable design with switching network interconnect is proposed for fast turn-around, low manufacturing cost, and layout-independent high-speed systems. We introduce the architecture and investigate the constraints and properties originated from the architecture. We show that routability is the most crucial concern for a successful design, and propose objective functions as well as algorithms for switching network optimization. The mapping for the circuits is performed by partitioning, placement, and routing using a maximum matching method. The integration of the whole system demonstrates excellent results in terms of circuit usage     

边界扫描SRAM簇板级互连测试研究

由于边界扫描结构的复杂与费用的关系,在现代电子电路中广泛使用的静态随机存取存储器还很少包含边界扫描结构.本文提出了一种能完全实现SRAM簇互连测试的方法,该方法能检测SRAM簇控制线、数据线和地址线的板级互连故障,且测试长度较短.     

50-GHz integrated interconnects in silicon optical microbench technology

A custom-designed silicon-based 50-GHz interconnect is integrated for packaging demonstrations of broadband optoelectronic (OE) applications in silicon optical microbench technology. The half-shielded (or partially shielded) 0.5-cm interconnect has 25-dB isolation and 0.9-dB transmission loss over 50 GHz. When implemented in this packaged architecture, the nature of the interconnect minimizes coupling and eliminates the need for an external test fixture that is prevalent in a more conventional approach. The interconnect is further demonstrated in a multiport electrical package to illustrate the potential of this architecture up to 40-Gb data rates, and the resulting package has insertion loss less than 5 dB at 50 GHz.     

Experimental single-chip PABX

Experimental VLSI techniques and an architectural concept are described which permit the realization of an experimental single-chip private automatic branch exchange (PABX) for switching voice and data. Analysis indicates that up to 40 telephones and 40 data terminals could be interconnected with a single chip. The architecture makes it possible to interconnect multiple PABX chips to form a larger system. The single-chip concept is made possible by distributed switching near the subscriber, digital interface, a new `orthogonal' RAM, and a low-power line-driving technique, all of which are included in this investigation.     

Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs

In this paper, we describe how a phase switching technique is used to control the harmonic contents of a generated sinusoidal signal using digital signal processing techniques. We will describe how this technique equalizes the harmonic performance of arbitrary waveform generators installed in a large scale integration test system, allowing extended performance testing of the total harmonic distortion of an analog-to-digital converter that ordinarily would be possible only using more advanced test equipment. Once a device has been characterized and correlated to the bench, a test engineer is required to release the product into production. One of the major issues surrounding this exercise is the difference in the obtained results between testers of the same manufacture for parameters sensitive to harmonics, noise, and spurious components such as total harmonic distortion. By using the techniques developed in this paper, the user will be able to deploy an academic solution to an industrial problem and extend the range of test equipment that ordinarily would need to be discarded for such test requirements. We will then show the gauge repeatability and reproducibility between two testers of the same manufacture, and how using the described technique produces a better correlation, thus allowing less stringent guard-bands to guarantee the performance of those devices that have performance criteria close to the device specification. This work also goes some way to proving previous papers’ works on distortion shaping testing to enhance the spectral performance of arbitrary waveform generators.     

Packet-by-packet wavelength-routing interconnect technique for 5Tbit/s switching system

A packet-by-packet wavelength-routing interconnect technique for a 5 Tbit/s switching system with a three-stage architecture has been demonstrated. The technique uses an optical wavelength division multiplexing (WDM) link and dynamic bandwidth-sharing among wavelengths. The inter-stage, electro-optical interconnection subsystem was fabricated using very compact 2.5 Gbit/s, eight-wavelength WDM transmitters/receivers and an arrayed-waveguide grating router     

基于多端口存储器互连结构的多处理器系统芯片设计

多处理器系统芯片设计的关键问题之一是微处理器之间的互连结构.在总线互连结构和开关互连结构之后,提出了基于多端口存储器的第3种互连结构.利用VHDL进行了多时钟多端口存储器设计,并利用EDA工具进行了片上系统芯片的多微处理器数据通讯的功能仿真.分析了基于总线、基于开关、基于多端口存储器的3种互连结构的特点.研究表明基于多端口存储器的互连结构具有异步数据传输,数据缓冲功能;具有数据传输延时小,多微处理器系统芯片的拓扑阵列规模可扩展的优点.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.