A programmable router architecture supporting control planeextensibility

The Internet is evolving from an infrastructure that provides basic communication services into a more sophisticated infrastructure that supports a wide range of electronic services such as virtual reality games and rich multimedia retrieval services. However, this evolution is happening only slowly, in part because the communication infrastructure is too rigid. In this article we present a programmable router architecture in which the control plane functionality of the router can be extended dynamically through the use of delegates. Delegates can control the behavior of the router through a well-defined control interface, allowing service providers and third-party software vendors to implement customized traffic control policies or protocols. We describe Darwin, a system that implements such an architecture. We emphasize the runtime environment the system provides for delegate execution and the programming interface the system exports to support delegates. We demonstrate the advantages of using this system with two delegate examples     

CSRouter：服务可扩展的路由器体系结构

互联网应用的发展促进了网络从面向端—端数据传输的"管道"向集成计算资源、存储资源和网络资源的"平台"模型的发展。以统一交换技术为基础的路由器系统区域网连接转发引擎、服务单元和存储单元等资源,建立了新型计算—存储—转发处理模型。基于NetMagic平台和IEF交换系统实现了CSRouter原型系统。报文缓存应用测试表明,路由器系统区域网能够在转发引擎和服务单元之间提供高带宽高可靠的互连,基于系统区域网的路由器能够利用计算资源和存储资源对IP报文进行深度处理,加速网络应用,增强路由器服务可扩展性。     

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.     

GMPLS-based photonic multilayer router (Hikari router)architecture: an overview of traffic engineering and signalingtechnology

A new extended signaling and traffic engineering method for the GMPLS-based photonic and electrical multilayer router (Hikari router) is proposed. The method allows dynamic optical network management and photonic signal recovery, such as regeneration, reshaping, etc., to be realized adaptively. Wavelength conversion is also adaptive, which reduces network cost. Multilayer traffic engineering, which yields the dynamic cooperation of IP and photonic layers, is described to provide IP services cost effectively. To realize multilayer traffic engineering, we propose the OSPF extension, which advertises both the number of total wavelengths and the number of unused wavelengths, and the RSVP-TE extension, which minimizes the number of wavelength conversions needed. In addition, this paper proposes a heuristics-based multilayer topology design scheme that uses IP traffic measurements in a generalized multi-protocol label switch (GMPLS). The proposed scheme yields the optical label switch path (OLSP) network topology, that is, OLSP placement, that minimizes network cost, in response to fluctuations in IP traffic demand. In other words, the OLSP network topology is dynamically reconfigured to match IP traffic demand. Networks are reconfigured by the proposed scheme so as to utilize network resources in the most cost effective manner     

线速路由器分组并行处理体系结构与性能分析

本文在分析路由器报文献处理需求的基础上,探讨了报文多处理模块并处理的体系结构,并以四个处理模块为例对分组处理时延做了定量分析和仿真。分析表明,当各模块处理能力总和与单独模块结构处理能力相同时,多模块结构处理时延将大于单模块结构;当各模块处理能力总和大于单处理模块结构处理能力的同时,系统处理的时延特性可得到明显改善,并且系统具有较好的可扩充性。     

一种实现LAR协议的路由器架构设计

LAR （Location-Aided Routing）协议是一种适用于无线移动自组网的路由协议.介绍了当前传统的路由器架构,实现LAR协议路由器的需求,并提出了一种实现LAR协议的、基于Linux架构的路由器架构设计.     

Design of programmable NoC router architecture on FPGA for multi-cluster NoCs

The next generations of massive, parallel and reconfigurable multi-cluster chips need performance and flexibility, requiring new communication schemes. According to this scenario, a programmable router architecture for networks-on-chips is presented. Results indicate that the proposed router has low area occupation, low power consumption and a high data throughput.     

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router

We propose a new CAM architecture for the large-scale integration and low-power operation of a network router application. This CAM reduces entry count by an average of 52%, using a newly developed one-hot-spot block code. This code eliminates redundancy in a memory cell and improves the efficiency of IP address compression. To implement the proposed code, a hierarchical match-line structure and an on-chip entry compression/extraction scheme are introduced. With this architecture, a search-depth control scheme deactivates unnecessary search lines and reduces power consumption by 45%. Using a DRAM cell, our new content addressable memory (CAM) can achieve 1.5 million entries in 0.13-/spl mu/m technology, which is six times more than a conventional static ternary CAM.     

A 50-Gb/s IP router

Aggressive research on gigabit-per-second networks has led to dramatic improvements in network transmission speeds. One result of these improvements has been to put pressure on router technology to keep pace. This paper describes a router, nearly completed, which is more than fast enough to keep up with the latest transmission technologies. The router has a backplane speed of 50 Gb/s and can forward tens of millions of packets per second     

BiLink: A high performance NoC router architecture using bi-directional link with double data rate

This paper presents a novel high performance Network-on-Chip (NoC) router architecture design using a bi-directional link with double data rate (BiLink). Ideally, it can provide as high as 2 times speed-up compared with the conventional NoC router. BiLink utilizes an extra link stage between routers and transmits two flits in one link per cycle using phase pipelining if both routers require to use the current link. To further increase the effective bandwidth, the direction of each link can be configured in every clock cycle to cater for different traffic loads from each side. Therefore, the data rate can be as high as 4 times compared with conventional NoC routers under uneven traffic. Centralized mode control scheme is implemented using a finite state machine (FSM) approach. Cycle-accurate simulations are carried out on both synthetic traffic patterns as well as real application benchmarks. Simulation results show that BiLink can provide as high as 90% and 250% speedup compared with conventional NoC routers for even and uneven traffic, respectively. 2X and 3X gains in throughput are obtained under even and uneven traffic, respectively, when compared with the conventional NoC router for the virtual channel flow control. The BiLink router architecture is synthesized using TSMC 65 nm process technology and it is shown that an area overhead of 28% over state-of-the-art bi-directional NoC is introduced while the critical path is about 9% higher than that of the conventional routers. Despite the overhead in critical path and power consumption, a 47.45% improvement of Energy-Delay-Product (EDP) is achieved by BiLink under high injection rate traffic.     

A subnanosecond polarization-independent tunable filter/wavelength router using a Sagnac interferometer

A high-speed, polarization independent, electrooptic tunable filter was built using a birefringence modulator within a Sagnac interferometer. Switching times less than 0.5 ns were achieved in our experiment for this filter. Application in highspeed wavelength routing was also demonstrated.     

面向多网络体制并存的开放式可重构路由器体系结构设计与实践

针对现有网络设备在支持可重构和多网络体制并存方面存在的不足,提出了一种面向多网络体制并存的开放式可重构路由器体系结构。通过在控制、转发和交换体系结构设计上,采用虚拟化和硬件分区配置技术,能够对控制、转发和交换进行资源划分与隔离,将路由器中同一个硬件资源虚拟化为多个功能上独立、资源上隔绝的逻辑路由器实例,提高了核心路由器设备的开放性和安全性。     

高端路由器主备同步技术的研究

高端路由器设备通常采用主备倒换来延长系统的可靠运行时间,而主备数据同步是实现主备倒换的关键技术。针对传统主备同步技术可靠性低,同步速率低的问题,提出了一种新的主备数据同步解决方案。新的主备同步方案使用了可靠的主备数据同步通道;提出给同步数据分类,并采用合适的方法同步。经实验验证,该技术方案应用在高端路由器上,提高了主备同步速率与可靠性,从而提高了系统性能,同时模块化的设计,具有很好的通用性,实现简单,实用性高。     

Hierarchical channel router

The channel routing problem is a special case of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle.We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 × n) grid and on consistent utilization of a ‘divide-and-conquer’ approach. For the current implementation of the algorithm, the running time is proportional to N 1 n log(m) where N is the number of nets, n the length of the channel (number of columns) and m the width of the channel (number of tracks).Traditional technological restrictions are assumed, i.e., net terminals are located on vertical grid lines, two wiring layers are available for interconnections — one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change.This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them — Deutsch's ‘difficult example’ — was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.     

SS/FDMA router for flexible satellite communications networks

The subchannel switched frequency-division multiple-access (SS/FDMA) system improve the routing flexibility of transponder banks in channelized multibeam satellites. This system can efficiently be utilised to construct a VSAT (very small aperture terminal) network and/or a business satellite communications network using small aperture terminals. The authors address the application of the SS/FDMA system to such networks. A proof-of-concept (POC) model of SS/FDMA onboard equipment called the SS/FDMA router is described in terms of its configuration and measured electrical performance. Results of transmission experiments using the POC model as well as computer simulations are presented. In addition, a redundant SS/FDMA router configuration is proposed, and its reliability is calculated for a 15-year satellite mission time. Finally, estimated values of volume, mass, and DC power consumption of the redundant SS/FDMA router are presented     

Power consumption analysis of a NetFPGA based router

For both economic and environmental reasons, energy efficiency is becoming increasingly important in the design of next generation networks (NGN). The energy efficiency improvements for network components can mainly be achieved by the support of smart standby and/or frequency scaling. This paper describes fine-grained power measurements of the peripheral component interconnect (PCI)-based network field-programmable gate array 1 gigabit (NetFPGA 1G) reference router when scaling the frequency of router core logic and static random access memories (SRAMs) between 125 MHz and 62.5 MHz. This paper presents the power consumption of a NetFPGA 1G reference router under different scenarios. Results show that by reducing the frequency from 125 MHz to 62.5 MHz, under a user datagram protocol (UDP) traffic load of 400 Mbit/s, 12.23% of power can be saved with the same quality of service (QoS), i.e. no packet loss in either case. Moreover, aggregating the traffic and rerouting the packets can save relatively high amount of energy. For example, our results show that 19.77% of power consumption can be saved by aggregating four 100 Mbit/s links into two 200 Mbit/s links.     

千兆位路由器的线卡设计

介绍了1Gb/s速率的核心路由器中线卡的体系结构,并从设计的角度对一些主要的功能模块进行了分析,详细论述了线卡转发引擎中基于FPGA的设计与实现,经过时序仿真与系统测试,验证了线卡设计的正确性.     

铣刀性能测试方法

随着无卤素及高Tg板材的应用,以及各装配厂家对尺寸及外观要求越来越高,PCB冲切工艺应用减少,均要求采用铣加工成型,虽然PCB行业所用原材料均有相应的标准,通过对应的检测方法,以达到检查原材料是否满足要求的目的;但因各个厂家加工条件及板材的不同,必须有一套适合自己公司的检测体系;为此,特对弊司铣刀性能及寿命测试过程中的要点进行总结,以达到后序测试过程程序化、规范化得目的。     

A radical new router

The Internet is broken. I should know: I designed it. In 1967, I wrote the first plan for the ancestor of today's Internet, the Advanced Research Projects Agency Network, or ARPANET, and then led the team that designed and built it. The main idea was to share the available network infrastructure by sending data as small, independent packets, which, though they might arrive at different times, would still generally make it to their destinations. The small computers that directed the data traffic-I called them Interface Message Processors, or IMPs-evolved into today?s routers, and for a long time they've kept up with the Net's phenomenal growth. Until now.