Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Elevated n+/p junctions by implant into CoSi2formed on selective epitaxy for deep submicron MOSFETs

Very shallow elevated n⁺/p junctions formed by arsenic implant into or through cobalt silicide (CoSi₂) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi₂ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi₂ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Experimental determination of electron drift velocity in 4H-SiC p+-n-n+ avalanche diodes

4H-SiC p⁺-n-n⁺ diodes of low series resistivity (<1×10^-4 Ω·cm²) were fabricated and packaged. The diodes exhibited homogeneous avalanche breakdown at voltages U_b=250-270 V according to the doping level of the n layer. The temperature coefficient of the breakdown voltage was measured to be 2.6×10^-4 k^-1 in the temperature range 300 to 573 K. These diodes were capable of dissipating a pulsed power density of 3.7 MW/cm² under avalanche current conditions. The transient thermal resistance of the diode was measured to be 0.6 K/W for a 100-ns pulse width, An experimental determination of the electron saturated drift velocity along the c-axis in 4H-SIC was performed for the first time, It was estimated to be 0.8×10⁷ cm/s at room temperature and 0.75×10⁷ cm/s at approximately 360 K     

Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

DC characteristics of high-breakdown-voltage p-i-n diodes made by20-MeV Si implantation in InP:Fe

A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n⁺ layer and a shallow p⁺ layer, respectively. The junction area of the device is 2.3×10^-5 cm² and the intrinsic region thickness is ≈3 μm. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm² at -80 V, off-state capacitance of 2.2 nF/cm² at -20 V, and a DC incremental forward resistance of 4 Ω at 40 mA     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

Low-temperature growth of silicon-boron layer as solid diffusionsource for polysilicon contacted p+-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p⁺-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF₂⁺-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF₂⁺ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 Å, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm² at -5 V were obtained. As the junction depth shrank to 300 Å, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm², respectively. These results demonstrated that a uniform ultrashallow p⁺-n junction can be obtained by using a thin Si-B layer as a diffusion source     

Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi2and n⁺-p⁺source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10^-7and 1 × 10^-6Ω . cm²can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10²⁰/cm³. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n⁺and TiSi2-P⁺interfaces.     

Characteristics of planar n-p junction diodes made bydouble-implantations into 4H-SiC

Double implantation technology consisting of deep-range acceptor followed by shallow-range donor implantation was used to fabricate planar n⁺-p junction diodes in 4H-SiC. Either Al or B was used as the acceptor species and N as the donor species with all implants performed at 700°C and annealed at 1650°C with an AlN encapsulant. The diodes were characterized for their current-voltage (I-V) and capacitance-voltage (C-V) behavior over the temperature range 25°C-400°C, and reverse recovery transient behavior over the temperature range 25°C-200°C. At room temperature, the B-implanted diodes exhibited a reverse leakage current of 5×10^-8 A/cm² at a reverse bias of -20 V and a carrier lifetime of 7.4 ns     

Characterization of shallow silicided junctions for sub-quartermicron ULSI technology. Extraction of silicidation induced Schottkycontact area

The current-voltage (I-V) characteristics of shallow silicided p ⁺-n and n⁺-p junctions are presented. In the former the diode behavior was same as in nonsilicided junction, while drastic change in diode I-V was observed in the latter. The formation of Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n⁺-p junction in the forward bias region. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, masking thereby the effect of Schottky contact. The leakage current in n⁺-p diodes was higher than in nonsilicided diodes by two orders of magnitude and this is consistent with the formation of Schottky contact via titanium or titanium-silicide penetrating into the p-substrate and generating trap sites. There is no increase in the leakage current and no formation of Schottky contact in case of the p⁺-n junction. The Schottky contact amounting to less than 0.01% of the total junction area and not amenable for SEM or TEM observation was extracted for the first time by simultaneous characterization of forward and reverse characteristics of silicided n ⁺-p diode     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

Nickel ohmic contacts to p and n-type 4H-SiC

The first demonstration of Ni ohmic contacts to both p⁺ and n⁺ 4H-SiC formed by ion implantation is reported. Sample preparation conditions are described and experimental results presented. Specific contact resistances in the range of 10^-4 Ω cm ² and 10^-6 Ω cm² for p⁺ and n⁺ 4H-SiC, respectively, have been determined by the transfer length method     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

The influence of Ge-implantation on the electrical characteristicsof the ultra-shallow junction formed by using silicide as a diffusionsource

The electrical characteristics of ultra-shallow p⁺/n junctions formed by implanting a 60 keV Ge⁺ into a TiSi₂ layer have been studied. A very low reverse leakage current density (≅0.4 nA/cm² at -5 V) and a very good forward ideality factor n (≅1.001) were achieved in these ultra-shallow p ⁺/n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 Å and the surface concentration was about 3 times higher than that of the conventional samples