100-V high-performance amplifiers in BCD technology for SLICapplications

The circuits described by the authors are a line driver and a sensing amplifier. They are part of a subscriber line interface circuits (SLIC) fabricated in BCD technology that operates up to 100 V. The driver requires about 500 μA of quiescent current, can sink and source up to 100 mA, and remains stable for all possible line lengths. The sensing amplifier senses the line current to synthesize both the AC and DC line terminations. It achieves a 2-mV offset and a gain-bandwidth product of 2.5 MHz. The adopted mixed technology allows the realization of a compact single-chip SLIC     

A CMOS SLIC with an automatic balancing hybrid

A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL.     

采用高压模拟／I^2L兼容工艺的用户线接口电路设计

本文分析了高压模拟/I~2L兼容工艺的特点,着重介绍了一种采用介质隔离高压模拟/I~2L兼容工艺的用户线接口电路的特点、工作原理、版图设计与工艺特点,电路内部含有二-四线转换,检测用户摘挂机功能以及过压、过流保护功能,电路可承受70V以上的高压。采用薄膜电阻,使得匹配电阻精度大大提高,改善了电路的性能。     

Integrated electronic subscriber line interface circuit with ringing on chip

A new high-voltage, dielectrically isolated, complementary bipolar technology has been used to integrate high-voltage functions of a subscriber line interface circuit (SLIC). This circuit, in conjunction with a complementary low-voltage junction isolated bipolar integrated circuit, implements most of the line interface functions required for digital telephone switches. Partitioning of the junctions is based on technology requirements, and the two chips are encapsulated in 28-pin package.     

A no-trimming SLIC two-chip set with coin telephone signalingfacilities

A subscriber line interface circuit (SLIC) two-chip set that eliminates off-chip functional trimming and integrates coin telephone set facilities as well as BORSCHT functions is described. The LSI chip set consists of (a) a subscriber interface IC fabricated using a 320-V dielectrically isolated bipolar process with on-chip thin-film resistors and double-layer metal, and (b) a subscriber processor IC with oversampling A-D/D-A converters and a microprogrammable digital signal processor (DSP), using a 1.6-μm CMOS process. Chip sizes are 5.5 mm×6.06 mm and 6.0 mm×5.7 mm, respectively. Using the two-chip set, an SLIC for a coin telephone set can be designed without using high-precision filter components or hybrid ICs with functional trimming     

A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLIC) and the line card controller, the denouncing of eight line status bits included.     

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.     

A monolithic subscriber line interface circuit [in bipolar technology]

A monolithic SLIC fabricated with high-voltage dielectric isolation (DI) technology has been proven to have excellent performance and requires a minimum of external circuitry. The SLIC provides battery feed, overvoltage protection (with some external devices), ringing control, supervision, and hybrid functions.     

Fully analogue LMS adaptive notch filter in BICMOS technology

A fully analogue adaptive notch filter for meter pulse applications in analogue subscriber line systems is presented. The filter is part of an integrated circuit which includes both low voltage subscriber line interface circuit- (SLIC)- and CODEC-filter functions. The effects of offset, noise, and transient behavior are investigated, and a linear model for stability analysis is derived. Fabricated in a 1 μm BiCMOS technology this circuit uses the benefits of accurate SC-filters, low offset comparators, and linear multipliers. Due to the adaptive approach the performance of the filter is independent of process deviations and temperature effects. The filter has been designed for an attenuation of 50 dB @ 12 or 16 kHz, a dynamic range of 103 dB and a settling time of less than 5 ms     

基于梯度的极化SAR图像超像素分割

超像素分割在图像分割领域以其优异的性能表现被广泛应用,准确性和高效性是评价分割性能的重要指标.简单线性迭代聚类（simple linear iterative clustering,SLIC）方法在光学图像上表现出了优异的性能,在极化合成孔径雷达（synthetic aperture radar,SAR）图像中也被广泛应用,然而SLIC方法中的初始化步骤不能准确地定位类中心,需要多次的迭代纠正误差.改进的分水岭方法（spatial constrained watershed,SCoW）是一种基于梯度阈值区分的简单且高效的分割方法,但是不能直接用于极化SAR图像.本文受SCoW的启发,提出一种对SLIC进行预处理的分割方法,通过横虚警（constant false alarm rate,CFAR）边缘检测器计算得到极化SAR图像的梯度信息,并将梯度信息用于初始化分割.基于两幅实测极化SAR图像,将本文提出方法与其他三种方法对比.实验表明本文方法可以减少整个算法的迭代次数,得到更加符合图像信息、贴合图像边界的分割结果.     

A broadband high-voltage SLIC for a splitter- and transformerlesscombined ADSL-Lite/POTS linecard

A monolithic broadband subscriber line interface circuit (B-SLIC) has been integrated in the smart power technology SPT170B, combining the functionality of an analog 150-V ringing SLIC with that of a line driver for ADSL-Lite data signals. Thus the B-SLIC is the key circuit for the realization of a very compact integrated voice data (IVD) central office linecard that neither needs analog filters (“POTS-splitter”) nor transformers or relays. In spite of the fundamental voltage/frequency tradeoff, the B-SLIC is able to feed high dc or ring voltages to the line, while simultaneously acting as voice and data transceiver. Total harmonic distortion values are below -60 dB even for a high 25-V_pp/550-kHz sine wave signal into a 200 Ω load; ADSL-signal-based multitone power ratio (MTPR) measurements also yield results better than 60 dB. Power dissipation in simultaneous voice and data operation is about 2.2 W     

A switching regulator and lightning protector for a subscriber line interface circuit

Two monolithic ICs, a switching regulator and a crowbar protector circuit fabricated in a 90-V complementary bipolar technology are described. These devices enhance the performance of a basic subscriber-line interface circuit (SLIC) by extending the range to the customer so that 20-mA DC feed current can be supplied to a 2800-/spl Omega/ loop without the need for a -72-V office battery. The power dissipation of the entire SLIC subsystem is at most 1.5 W for any length of subscriber loop. All circuitry is robustly protected from foreign 60-Hz and lightning voltages.     

A segmentation-based lossless image coding method forhigh-resolution medical image compression

Lossless compression techniques are essential in archival and communication of medical images. Here, a new segmentation-based lossless image coding (SLIC) method is proposed, which is based on a simple but efficient region growing procedure. The embedded region growing procedure produces an adaptive scanning pattern for the image with the help of a very-few-bits-needed discontinuity index map. Along with this scanning pattern, an error image data part with a very small dynamic range is generated. Both the error image data and the discontinuity index map data parts are then encoded by the Joint Bi-level Image Experts Group (JBIG) method. The SLIC method resulted in, on the average, lossless compression to about 1.6 b/pixel from 8 b, and to about 2.9 b/pixel from 10 b with a database of ten high-resolution digitized chest and breast images. In comparison with direct coding by JBIG, Joint Photographic Experts Group (JPEG), hierarchical interpolation (HINT), and two-dimensional Burg prediction plus Huffman error coding methods, the SLIC method performed better by 4% to 28% on the database used     

基于PC-MSPCNN模型和SLIC的彩色图像分割方法

针对简单线性迭代聚类(SLIC)方法对图像边缘细节处理效果不佳的问题,提出一种参数可控、改进的简化脉冲耦合神经网络模型(PC-MSPCNN)与SLIC结合的彩色图像分割方法。该方法首先改进MSPCNN模型的加权矩阵和连接系数,并增设辅助参数,以提高分割准确度。随后将彩色图像输入至PC-MSPCNN模型中,依据改进模型中输出Y值的分布划分物体的边缘,使分割结果更好地贴合物体的边缘,利用所提出的相似性准则合并散布的碎片,减小后续处理的复杂度;其次,在SLIC度量相似距离的基础上引入PC-MSPCNN中RGB三个通道的内部活动项U值,完成对图像剩余部分的加权融合聚类,改进聚类效果。实验结果表明,本文方法能更精确地贴合图像中物体的边界,大幅减少碎片,有效提高图像的边缘贴合度。     

基于SLIC超像素分割的SAR图像海陆分割算法

海陆分割在合成孔径雷达(SAR)图像的海面目标检测以及海岸线提取等海洋应用方面具有非常重要的意义。针对合成孔径雷达图像的特点,提出了基于SLIC超像素分割的SAR图像海陆分割算法。首先为抑制SAR图像固有相干斑噪声并较好地保留图像的边缘信息,采用精致Lee滤波对图像进行预处理。然后对图像进行SLIC超像素分割,再将分割后的图像进行FT区域显著性检测以及显著值相似度聚类。最后将处理后的图片二值化得到海陆分割结果。实验结果表明,本文所提海陆分割算法具有很高的处理精度以及较高的处理效率。     

融合相干/非相干信息的高分辨率SAR图像变化检测

该文运用Dempster-Shafer(D-S)证据理论融合高分辨率SAR影像的相干/非相干差异特征进行变化检测。首先使用简单线性迭代聚类(SLIC)分割算法完成多时相SAR影像联合多尺度分割。然后在各个分割尺度上提取适宜的强度差异特征及相干差异特征,通过Mean算子融合多尺度差异特征并得到多特征差异图。最后运用D-S证据理论完成多特征差异图融合得到变化检测结果。实验表明该方法可得到较为稳健的变化检测结果。      

用户线接口电路PBL38710/1及其应用

对用户线接口电路(SLIC)PBL38710／1的工作原理和主要特性进行介绍，并给出应用电路。     

SOPHO—S2500系统硬件结构剖析

ＳＯＰＨＯ－Ｓ２５００是ＳＯＰＨＯ－Ｓ系列中容量最大的交换机。本文介绍了ＳＯＰＨＯ－Ｓ２５００系统的功能模块组成和专用大规模集成电路，并剖析了各功能模块的硬件结构。     

Bipolar transistor modeling of avalanche generation for computer circuit simulation

An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.