共查询到19条相似文献,搜索用时 187 毫秒
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储奕锋 《数字社区&智能家居》2007,(10):191-193
本文介绍了AES数据加密结构,以及相关的有限域的知识及简单运算,提出了一种用FPGA高速实现AES算法的方案,该方案设计的加密模块支持AES标准的三种密钥长度:128,192,256,支持ECB,CBC,CTR三种工作模式,即支持feedback和non-feedback两种模式,最后给出了本设计的性能指标。通过比较国内外相关测试数据,该方案在功能和速度(吞吐率)上均取得了较优的性能。 相似文献
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结合对称密码算法中的DES、IDEA、AES和单向散列算法中的MD5、SHA-1、SHA-256等算法,提出了一种在同一文件内部采用多模式加密的方案,该方案比传统的单一模式加密的方案能更好地保证数据的完整性和安全性.详细描述了该方案的算法实现,通过试验验证了其实用性,同时分析了该方案的优点和不足. 相似文献
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资源共享的并行AES加密/解密算法及其实现 总被引:2,自引:1,他引:2
随着密码分析技术的提高,原有的数据加密标准(DES)已经不能满足应用的要求.高级加密标准(AES)成为新一代的数据加密标准,取代了使用20多年的DES.目前的AES算法实现中普遍存在资源消耗大或者吞吐率低以及加密和解密分别实现的不足.为在资源消耗和吞吐率之问取得折衷,以资源共享和并行的方式同时实现AES加密和解密算法,分析AES算法中各个变换以及128位密钥扩展的性质和特点,选择复合域优化字节置换变换.推导结构简化列字节混合变换,提出128位加密/等效解密密钥扩展方案,同时实现了资源共享的并行AES加密和解密算法.通过在FTGA上的验证和与相关文献的比较,表明该方案以较少的资源获得了较高的吞吐率. 相似文献
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针对高级加密标准(Advanced Encryption Standard,AES)算法需要兼容不同工作模式以及不同密钥长度的加密需求,提出全通用AES加密算法。该算法通过设计可调节密钥扩展模块和模式选择模块,实现128/192/256位宽的加密,支持ECB/CBC/CFB/OFB/CTR 5种工作模式。基于Xilinx公司的XC7VX690T FPGA综合仿真,资源消耗为1 947 Slices,最高工作频率为348.191 MHz。 相似文献
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新一代WLAN安全标准IEEE 802.11 i定义了三种协议来保护数据的传输,这三种协议增强了WLAN中数据的加密和鉴别性能,取代了IEEE 802.11 WEP方案。CCMP协议是数据保密协议之一。CCMP协议使用基于AES的加密算法和CCM加密鉴别模式,在软件和硬件实现上都提供了很好的安全性能。 相似文献
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介绍了AES数据加密结构,以及相关的有限域的知识及简单运算,提出了一种用FPGA高速实现AES算法的方案。AES加密算法密码模块作为安全保密系统的重要组成部分,其核心任务就是加密数据。AES以其高效率、低开销、实现简单等特点被广泛应用于密码模块的研制中。 相似文献
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借鉴国外已有的移动交易支付模式,结合我国金融系统的特点及安全要求,提出了一种基于改进的3-D Secure协议的移动支付安全方案,该方案采用AES(Advanced Encryption Standard)算法对通信报文加密,通过一套支持多信道报文安全传输控制的安全认证体系,来保证在移动支付业务中的客户、商户和资金信息... 相似文献
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With each passing day, Internet of Things (IoT), has the potential to transform our society to a more digital way. In this paper, a cryptographic system is proposed, which has been designed and implemented, following the IoT optimized technologies. As the benefits of IoT are numerous, the need for a privacy platform is more than necessary to be developed. This work aims to demonstrate this by, firstly, implementing efficient and flexible, the fundamentals primitives of cryptography and privacy. Secondly, this is achieved, by introducing applied cryptography, in a more interactive and flexible approach. The proposed system and the incorporation of this platform is scrutinized. In the context of this work, an application of symmetric cryptography is introduced, based on the Advanced Encryption Standard (AES) in Electronic Code Book (ECB), Cipher Block Chaining (CBC) and Counter (CTR) modes of operation, for both encryption and decryption of texts, images and electronic data applications. In addition two other security schemes are supported by the proposed system: AES Galois/Counter Mode (GCM) and AES Galois Message Authentication Code (GMAC). The GCM proposed integration, in an authentication scheme, designed to provide authenticity and confidentiality, at the same time. On the other hand, GMAC, can be applied as message authentication code. Both operations, are optimized in sense of implementation resources, since the major cost is targeted to AES core. In addition, based on the integrated hardware modules, user registration and validation is proposed and implemented, with no additional cost, and with no performance penalty. Furthermore, two factor authentication has been designed and proposed, based on One Time Passwords (OTP), which can been produced with a random procedure. After these, a reference to the security levels, as regards to the communication between the IoT layers of the architecture, is presented. IoT hardware platforms are facing lack of security level and this brings the opportunity to use advanced security mechanisms. Implementation comparison results emphasize the importance of testing and measuring the performance of the alternative encryption algorithms, supported by hardware platforms. 相似文献
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在智能卡、PDA等便携式设备中,希望使用面积小的密码芯片。通过对AES算法进行结构优化,有效地减小了硬件实现时的开销。使用Verilog HDL语言设计并在Altera APEX20K器件中验证通过,设计集成了加密/解密模式及所有3种密钥长度,为进一步的VLSI实现提供了FPGA原形验证。 相似文献
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分组密码工作模式的研究现状 总被引:16,自引:0,他引:16
分组密码工作模式是利用分组密码解决实际问题的密码方案.好的工作模式可以弥补分组密码的某些缺憾;相反,不好的工作模式可能带来安全隐患.工作模式的研究始终伴随着分组密码的研究历史,新的分组密码标准的推出,都会伴随着相应工作模式的研究.从针对DES的ECB、CBC、CFB和OFB,到针对AES的CTR、CCM、CMAC、GCM和AESKW,作者以各种模式标准为主线,介绍分组密码工作模式的设计理念、安全模型、二十多年的研究成果以及发展现状. 相似文献
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Stefaan Mys Jürgen Slowack Jozef Škorupa Nikos Deligiannis Peter Lambert Adrian Munteanu Rik Van de Walle 《Multimedia Tools and Applications》2012,58(1):239-266
Distributed Video Coding (DVC) is a video coding paradigm in which the computational complexity is shifted from the encoder
to the decoder. DVC is based on information theoretic results suggesting that, under ideal conditions, the same rate-distortion
performance can be achieved as for traditional video codecs. In practice however, there is still a significant performance
gap between the two coding architectures. One of the main reasons for this gap is the lack of multiple coding modes in current
DVC solutions. In this paper, we propose a block-based distributed video codec that supports three coding modes: Wyner–Ziv,
skip, and intra. The mode decision process is entirely decoder-driven. Skip blocks are selected based on the estimated accuracy
of the side information. The choice between intra and Wyner–Ziv coding modes is made on a rate-distortion basis, by selecting
the coding mode with the lowest rate while assuring equal distortion for both modes. Experimental results illustrate that
the proposed block-based architecture has some advantages over classical bitplane-based approaches. Introducing skip and intra
coded blocks yields average bitrate gains of up to 33.7% over our basic configuration supporting Wyner–Ziv mode only, and
up to 29.7% over the reference bitplane-based DISCOVER codec. 相似文献
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由于对广泛使用的AES算法的性能要求越来越高,基于软件的密码算法已经越来越难以满足高吞吐量密码破解的需求,因此越来越多的算法利用现场可编程逻辑门阵列(FPGA)平台进行加速。针对AES算法在FPGA硬件上存在的开发复杂度高且开发周期长等问题,采用高层次综合(HLS)设计方法,使用高级程序语言描述并设计AES硬件加速算法。首先利用循环展开等提高运算并行度;其次使用资源平衡技术进行优化,充分利用片上存储和电路资源;最后添加全流水结构,提高整体设计的时钟频率和吞吐量,同时也详细对比分析基准设计、利用结构展开、资源均衡以及流水线优化方法的设计。经过实验表明,在Xilinx xc7z020clg484 FPGA芯片上,最终AES算法的时钟频率最高达到127.06 MHz,而吞吐量达到了16.26 Gb/s,较之基准的AES设计,性能提升了三个数量级。 相似文献
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随着大数据的发展及加密场景的增多,仅以软件运行的加密方式难以满足加密性能的需求;而使用Verilog/VHDL方式实现的FPGA/ASIC加密系统又存在灵活性较差、维护升级困难等问题。针对上述问题,设计并实现了一种基于异构可重构计算的AES算法加密系统,包含了AES算法ECB、CBC、CTR三种主流模式,每种模式实现了128 bit、192 bit、256 bit三种密钥大小的加密。基于FPGA对模块分别进行了硬件加速,同时基于硬件可重构机制实现了不同模式及不同位宽加密模块的动态切换。通过在Intel Stratix 10上实现并验证该系统,实验结果表明:系统中AES-ECB、AES-CTR、AES-CBC吞吐率分别达到116.43 Gbps、60.34 Gbps、4.32 Gbps,ECB模式相比于Intel Xeon E5-2650 V2 CPU和Nvidia GeForce GTX 1080 GPU分别获得了23.18倍与1.43倍的加速比,整体系统相比纯软件方式的计算加速比达到4.72。 相似文献
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This paper offers a high-level retrospective overview of the GOPI middleware platform which is the outcome of a three-year
project aimed at the development of generic, configurable and extensible middleware. GOPI has a clearly defined modular structure,
is widely extensible with plug-ins at all levels of the architecture, and natively supports stream interactions as well as
standard operation invocation. It offers a generic framework for quality of service (QoS) specification and management, and
supports a high-level, multimedia-oriented programming environment that is backwardly compatible with the OMG's CORBA. At
its lower levels it supports QoS-driven resource management and features an optimised IIOP stack. Despite its enhanced functionality,
GOPI's IIOP performance equals or exceeds that of state-of-the-art CORBA platforms.
Correspondence to:G. Coulson (e-mail: geoff@comp.lancs.ac.uk) 相似文献