Threshold I/SUP 2/L and its applications to binary symmetric functions and multivalued logic

I/SUP 2/L threshold gate using current mirrors providing weighting of inputs, summation, and comparison with a threshold is described and its practical realization is discussed. Application to binary symmetric functions shows significant area savings over standard I/SUP 2/L implementation. A complete multivalued logic family, using a four-level I/SUP 2/L threshold logic technique is introduced.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

Folded-collector integrated injection logic

Folded-collector I/SUP 2/L offers an effective method of controlling the saturation of the n-p-n transistor simply by controlling the ratio of two areas: the area of the output collector(s) and the area of a `dummy' collector. This extra collector is folded back and connected to the input base. The structure improves the minimum delay of the basic I/SUP 2/L gate. Moreover, the structure has many circuit applications where a current scaling factor is required, e.g., threshold and ternary logic. Some of these circuits are given.     

Current hogging injection logic-a new logic with high functional density

A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.     

Integrated injection logic-present and future

Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic is presented. A possible way of producing faster circuits is proposed.     

Computer-aided design of large-scale integrated I/SUP 2/L logic circuits

Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, computer simulation of I/SUP 2/L logic circuits, interconnection pattern generation, and preparation of a final layout plan.     

Modelling and optimization of the oxide isolated substrate fed I/SUP 2/L structure

A large-signal model is derived for the substrate fed integrated injection logic (I/SUP 2/L) gate which is suitable for computer-aided circuit design and the optimization of the physical structure. Since the analysis extends the Ebers-Moll model it differs from the existing models in that the effects of high-level injection and injector debiasing are included. Furthermore, heavy doping effects are included in the calculation of currents and minority carrier storage. The analysis of the oxide isolated structure predicts circuit delays of less than 5 ns at 50 /spl mu/A.     

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.     

A vertical injection logic watch IC with CMOS equivalent current drain

Vertical injection logic (VIL), an improved structure of I/SUP 2/L, was applied to an analog watch IC with a 1.5-V supply voltage, which resulted in a CMOS equivalent current drain of 2 /spl mu/A and half the chip size of CMOS. The design consideration and experimental work that support the characteristics are described.     

Substrate fed logic

A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product. The basic logic element is a multi-input, multi-output gate, formed in a single-base land by using several diffused collectors and several Schottky base contacts. The lateral p-n-p injector of conventional I/SUP 2/L has been replaced by a vertical arrangement. Factors affecting packing density and power-delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. A preliminary process to demonstrate the feasibility of the vertical injector is described and the measured transistor parameters and power-delay product are given. Experiments to determine suitable conditions for the formation of Schottky barrier diodes are presented, and satisfactory performance for the complete process is demonstrated.     

Integrated injection logic: a new approach to LSI

Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 /spl mu/m. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).     

Complementary DMOS process for LSI

This paper describes a new complementary metal-oxide semiconductor (CMOS) integrated circuit technology that utilizes a symmetrical double-diffused n-channel transistor. The features of the technology are the use of five masks, a self-aligned p-well diffusion and short channel n-MOS transistors. This results in a fifty percent reduction in p-well area as compared to conventional CMOS devices and lowers processing costs. Integrated circuits, fabricated using boron implantation for the p-well dose and p/SUP +/ diffusion, and arsenic implantation for the n/SUP +/ diffusion, exhibit a p-channel threshold of -1.8 V and an n-channel threshold of 1.2 V. The n-channel threshold is controlled by an initial boron implant of 3/spl times/10/SUP 14/ cm/SUP -2/ and subsequent double-diffusion steps. An invertor chain of seven cells bas been operated with a supply of 3-11 V. In operation, the delay per stage was 13 ns at 5 V and 5 ns at 10 V.     

Schottky I/SUP 2/L

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.     

Injection-coupled synchronous logic

A novel injector structure used in conjunction with an I/SUP 2/L gate is proposed and its application to the design of current comparators and synchronous logic is described. The operation and fabrication of basic gates as well as current comparators, SR and T flip-flops are discussed. The new gate structures exhibit similar power/spl times/delay products, but lead to a considerable increase in functional density when compared to standard I/SUP 2/L in synchronous logic applications.     

Bipolar structures for BIMOS technologies

Recent advances in LSI and VLSI have offered many possibilities in mixing MOSFET and bipolar integrated structures on the same chip. The authors study the integration of bi-polar structures in BIMOS environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology, e.g., the nonexistence of an n/SUP +/ underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip, and uses the epitaxial (substrate) resistance as a load. It can be used to realize logic and memory functions. Computer simulation as well as experimental results show that the structure can perform efficiently in both BIMOS and bipolar technologies.     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

DC analysis of multiple collector and multiple emitter transistors in integrated structures

A generalized set of equations has been developed for the multiple collector and multiple emitter transistors. These equations are applicable to the lateral transistors, SCR's, and the T/SUP 2/L coupling transistors. The analysis shows how a nonuniform base layer (double-epitaxial structure) can increase the alpha of the lateral transistor and decrease the current drain to the substrate and decrease the current drain to the substrate. The analysis also shows that in a T/SUP 2/L gate the inverse alpha is nearly equal to the cross-coupling current ratio, and can be reduced by increasing the number of inputs.     

ISL, a fast and dense low-power logic, made in a standard Schottky process

Integrated Schottky logic (ISL) is a new 200 mV voltage-swing LSI logic that can be made in standard Schottky processes with a double-layer metallization. It fills the gap between low-power Schottky TTL and I/SUP 2/L for those circuits where low-power Schottky TTL consumes too much power and takes up too much chip area, and when I/SUP 2/L does not attain the required speed. An ISL gate consists of a current source and a set of Schottky output diodes (wired AND gate). Minimum propagation delay times of 2.7 ns at 200 /spl mu/A/gate are obtained, with a speed-power product of 1.2 pJ. The packing density of ISL is 120 to 180 gates/mm/SUP 2/. The logic can be combined with ECL, I/SUP 2/L, and TTL on the same chip, and can also be made in analog processes.     

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.