V-groove substrate fed logic

A new substrate fed logic structure is presented which makes use of V-groove silicon etching. Experimental results are presented for the devices. A speed-power product below 1 pJ was obtained despite the large area of the test structures and the use of conventional bipolar processing. Further improvement in performance is expected by optimising the process parameters.     

Experimental realisation of a full adder by substrate fed threshold logic structure

A full adder has been designed and fabricated utilising substrate fed threshold logic. The internal operation is performed by four-valued threshold currents while the input and output signals are of binary form. The delay times of the experimental circuit operating with 10 ?A per injection window have been measured as 5 ?s for the sums and 1 ?s for the carry.     

Substrate fed logic

A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product. The basic logic element is a multi-input, multi-output gate, formed in a single-base land by using several diffused collectors and several Schottky base contacts. The lateral p-n-p injector of conventional I/SUP 2/L has been replaced by a vertical arrangement. Factors affecting packing density and power-delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. A preliminary process to demonstrate the feasibility of the vertical injector is described and the measured transistor parameters and power-delay product are given. Experiments to determine suitable conditions for the formation of Schottky barrier diodes are presented, and satisfactory performance for the complete process is demonstrated.     

Efficient realisation of MOS-NDR threshold logic gates

A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure.     

Domino logic with variable threshold voltage keeper

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.     

可编程实时光电混合阈值逻辑处理器

提出一种可编程实时光电混合阈值逻辑处理器,讨论了该处理器在数字光计算及光信息处理中的应用。     

A four-variable programmable universal logic module using digital summation threshold logic gates

Combining the concepts of programmable logic arrays (PLAs) and conventional universal logic modules (ULMs) a new type of programmable ULM for four variables has been proposed. The realization is based on the digital summation threshold logic (DSTL) gates, a cellular array for realizing threshold logic functions.     

The use of threshold logic in character recognition

The fact that many complex counting and decision functions can be realized quite simply with threshold gates suggests that they may be used to considerable advantage in problems of character recognition. A simplified recognition problem is considered involving the identification of any one of 12 letters when it is superimposed on an m × n matrix. Translation, stretching, and compression of the letter are permitted. It is shown that the number of threshold gates required increases linearly as do the dimensions of the matrix with about 300 gates being necessary for a 20 × 20. On such a matrix, several hundred thousand configurations of the 12 letters can be correctly identified with each pattern being insensitive to varying degrees of "noise." A threshold gate having the necessary fan power for this application is described together with its implementation in a small experimental model. Extensions of the methods to include rotation and magnification are discussed.     

Static hazards in combinational threshold logic networks†

The possibility of transitory false outputs in conventional digital logic circuits is well known, such output ‘ spikes ’ being the result of different propagation times through the logic network from inputs to output. The usual solution to such ‘ Static hazards ’ is also well known, being the incorporation of additional gates in the system to cover such input transitions. This paper shows that the application of threshold logic gates to logic synthesis has attractions in very easily eliminating such hazards, in many cases without the need for any additional covering gates in the network.     

An integrated m-out-of-n detection circuit using threshold logic

The design of the integrated 4-out-of-9 detector is based on a threshold logic approach. A differential current-switching circuit configuration is used, and the detector is fully compatible with conventional emitter-coupled logic (ECL). The circuit has a propagation delay of 16 ns and dissipates only 100 mW. The functional power-delay product of 1600 pJ is an order of magnitude below that achieved with an efficient gate design.     

Weighted sum threshold logic operation of MOBILE(monostable-bistable transition logic element) using resonant-tunnelingtransistors

The functional operation of the MOBILE (monostable-bistable transition logic element) has been studied using multiple-input logic gates. The MOBILE uses two resonant-tunneling transistors (RTTs) connected in series and driven by an oscillating bias voltage to produce a mono-to-bistable transition of the circuit. A MOBILE having three input gates with a 1:2:4 width ratio can distinguish all 8 (2³) input patterns corresponding to each weighted sum, depending on the threshold value selected by the control gate. The results confirm the realization of the weighted sum threshold logic operation of input signals     

A voltage tunable threshold logic gate based on multiquantum-wellheterojunction bipolar transistor for multifunction logic

The properties of a heterojunction bipolar transistor with a multiquantum-well collector region for its application as a voltage tunable logic element are examined. The quantum confined Stark effect gives rise to a strong negative differential resistance in the photocurrent-voltage characteristic of the device, which allows the device to be switched optically and/or electronically. This permits the realization of a circuit where the NAND, INVERSE CARRY, and NOR logic functions can be implemented by simply changing the biasing     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

Multi-threshold threshold logic circuit design using resonant tunnelling devices

A novel and extremely compact circuit topology able to implement a generalised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.     

Pass-transistor based implementations of threshold logic gates for WOS filtering

This paper presents a systematic procedure to implement threshold functions by using a pass-transistor network. A main feature of the threshold gates (TGs) produced by this technique is that they do not exhibit the fan-in limitations usual when other implementation techniques are used. Thus, they are especially useful for Weighted Order Statistical (WOS) filters because the binary filters required are threshold functions which usually present a high total sum of weights. A WOS filter with its binary filters implemented as pass-transistor TGs is demonstrated in an standard 0.35 μm CMOS technology at 3.3 V. The filter shows a sample frequency well over 100 MHz at the nominal process condition and it is cheaper, faster and consumes less power than a conventional approach.     

基板材料对光学薄膜近红外激光损伤阈值的影响

以电子束及电阻热蒸发镀制的TiO2、ZrO2、SiO2、MgF2、ZnS等单层膜及TiO2/SiO2多层膜为例,实验研究了熔石英(SiO2)、蓝宝石(Al2O3)以及氟化钙(CaF2)等不同基板材料对光学薄膜近红外激光损伤阈值的影响,结果发现,对单层膜及增透膜,基板材料对损伤阈值有较为显著的影响,其一般规律是阈值随基板热导率的提高而提高,而对高反膜,基板材料则无甚影响。文章结合体/面吸收研究以及损伤瞬态行为分析,用局部吸收导致热破坏这一机理,较好地解释了上述现象。     

Schottky I/SUP 2/L (substrate fed logic)-an analysis of the implications of the vertical injector structure and Schottky collection

The DC behavior of a Schottky I/SUP 2/L gate is analysed by using the Ebers-Moll equations, modified to include Schottky diodes. The usual definition of I/SUP 2/L common emitter current gain is replaced by a new definition which is more suitable for the vertical injector structure of Schottky I/SUP 2/L. The analysis is general and can be applied to any multijunction structure containing Schottky diodes or having a distributed current source. This framework is used to examine the effect on the fan-out of minority carrier collection at the Schottky contacts. Equations are presented which relate both the recombination at the Schottky contacts and the vertical reinjection through the inverse p-n-p transistor to the device structure.     

Low depth, low power carry lookahead adders using threshold logic

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.     

Dynamic threshold pass-transistor logic for improved delay at lowerpower supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed     

Novel universal threshold logic gate based on RTD and its application

Resonant tunneling diodes (RTDs) are receiving much attention because of their high-speed switching capability and functional versatility. Due to the negative differential resistance exhibited by RTDs, great functionality with a single gate can be achieved. In this paper, novel universal threshold logic gates (UTLG) based on RTD with simple structure and fixed parameter are proposed. The three-variable UTLG implement all the threshold functions of three variables by reconfiguring the input bits. The proposed circuit can also be applied to the design of arbitrary logic function in a multilevel threshold network. Finally, the operation of UTLG is verified by HSPICE simulation using extensively validated models.