A new photo-sensitive voltage-controlled differential negative resistance device—The lambda bipolar photo-transistor

A new photo-sensitive voltage-controlled differential negative resistance device called the LAMBDA bipolar photo-transistor is presented. The basic structure of the Lambda bipolar photo-transistor consists of the simultaneous integration of a bipolar junction transistor and a merged metal-oxide-semiconductor field effect transistor. The IV characteristic of this new device will exhibit a voltage-controlled differential negative resistance when the device is exposed to light. The operational principle of this new device will be described and the characteristics of the fabricated device are discussed.     

A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

A new integrated voltage-controlled negative resistance device-Lambda MOSFET

A new Λ-type voltage-controlled negative resistance device called the “Lambda MOSFET” is presented, which consists of three integrated n(p)-channel enhancement mode metal-oxide-silicon field effect transistors. The main integrated circuit construction of the Lambda MOSFET is to connect an inverter of the n(p)-channel enhancement mode MOSFET with load operated at the saturation region (NELS) and a n(p)-MOS driver, which can be easily fabricated by existing planar MOSFET technologies. The operational principles and the characteristics of the proposed new device are discussed.     

The SINFET—A Schottky injection MOS-gated power transistor

A new MOS-gated power device, the Schottky injection FET (SINFET), is described in this paper. The device offers 6 times higher current handling capability than conventional n-channel power LDMOS transistors of comparable size and voltage capability and still maintains a comparable switching speed. The low on-resistance is obtained by conductivity modulation of the high-resistivity n- drift region using a Schottky injector. Since only a small number of minority carriers are injected, the speed of the device is not degraded substantially and high latchup resistance is achieved. Breakdown voltages and specific on-resistance observed on typical devices are 170 V and 0.01 Ω . cm², respectively. Gate-turn off times are of the order of 30 ns. Two-dimensional simulation and experimental results comparing the SIN-FET with the LDMOST and lateral insulated gate transistor (LIGT) are presented.     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

A field-effect transistor with a negative differential resistance

We report the effect of negative differential resistance (NDR) in the drain circuit of a new type of selectively doped AlGaAs/ GaAs heterojunction transistor. The key new element of our structure is the presence of a subsidiary GaAs conducting layer, separated from the FET channel by an AlGaAs graded barrier. In this work the subsidiary layer is realized by the conducting substrate. The NDR effect arises due to the heating of channel electrons by the source-to-drain field, and the subsequent charge injection over the barrier. This effect is strongly influenced by the gate and substrate voltages. In a floating-substrate arrangement the current-voltage characteristics exhibit memory effects associated with retention of injected charge in the substrate. In this mode, the NDR is seen only at low temperatures with the peak-to-valley ratios in current at 77 K reaching values as high as 30. On the other hand, when the substrate is biased positively, the NDR results from a peculiar effect of dynamical channel depletion by the injected space charge which drifts on the downhill slope of the graded barrier. In this case, the NDR is observed even at room temperature.     

The nesistor—A semiconductor negative resistance device

A semiconductor device similar in principle to the injecting-drain-field-effect transistor, having wide ranges of controllable negative resistance which can be used in counting, flip-flop, amplifying, and oscillator circuits, is described. The negative resistance arises from the modulation of the current between two ohmic contacts of circular symmetry, on a flat semiconductor wafer, by the effect of the collection of minority carriers on the pinching potential of a collector electrode. Families of negative resistance, of either the shunt or series type, are obtainable depending upon the mode of operation. Power gains of 60 and thermal dissipation of 1/4 watt have been achieved in liquid cooled units the size of high-frequency transistors. An improved sandwich-type base tab for mounting semiconductor wafers is shown. A theoretical analysis of the operation of the device permits prediction of the effect of various physical parameters upon the static electrical characteristics.     

A new bipolar transistor—GAT

A new bipolar transistor named Gate Associated Transistor (GAT) was proposed and the operating mechanisms were verified. The structure of the GAT has a unique base region consisting of an FET merged into the base of a standard bipolar transistor. The operating mechanisms and characteristics of the GAT were investigated and compared with those of standard power transistors. The most outstanding feature of the GAT was a large area for safe operation.     

A new MOS-gate bipolar transistor for power switches

A new monolithic integrated power device, the MOS-gate transistor (MGT), which consists of a bipolar transistor for an output stage and two MOSFET's for a driver stage, has been investigated. The purpose of the study was to obtain a power switch having characteristics of an easy drive, a short turn-off time, and a high current density. The developed device structure featured the integration of three elements into a small cell from a large number of which the MGT chip was constructed. This device had no parasitic thyristor, making it free from the latchup phenomenon. Unit MGT devices with a blocking voltage of 400-500 V were fabricated. A high current density of 90 A/cm²at a collector-emitter voltage of 2 V and a short turn-off time of less than 1 µs were obtained. The MGT devices, which contained 36 cells, were fabricated with chip sizes of 5 × 5 mm. They exhibited a blocking voltage of 500 V, on-state voltage of 2.3 V at a current of 10 A, and turn-off time of 0.5 µs at 150°C.     

The MGBT: a new MOS-gated power bipolar transistor

A new device called the MGBT is described in which the upper regions of the device structure are conductivity-modulated by a positive feedback mechanism to give a lower on-state voltage drop compared to a power DMOSFET while having fast switching and fully gate-controlled characteristics. In the MGBT, a P⁺ injector coupled to the drain potential by a vertical driver DMOSFET in an emitter-switched configuration is used to inject holes which is then diverted to the entire surface region of the device by a novel cell design. 750 V MGBT devices fabricated along with DMOSFET devices on the same wafer showed 33% improvement in current density at room temperature and 46% improvement at 75°C at a forward drop of 3.5 V. The turn-off time of the MGBT was 80 ns equal to that of the DMOSFET     

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.     

A lateral metal—insulator—p-Si tunnel transistor

We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.     

The Laddertron—A new millimeter wave power oscillator

The Laddertron is a multi-gap klystron using ladders. This paper describes the theory and experimental results of the tube. Two types of Laddertrons are distinguished, namely theO-mode Laddertron and the π-mode Laddertron. The operation of each is analyzed and the equivalent circuit representations determined theoretically, whereby one can compute the resonant frequencies within an error of several per cent. A demountable experimental version of the π-mode Laddertron gave an output power of 10 watts for the 50-Gc band, an electronic tuning range of 300 Mc, and a mechanical tuning range of 2.5 Gc.     

Gummel plot nonlinearities in polysilicon emitter transistors—Including negative differential resistance behavior

The effects of a thin interfacial insulating layer between the deposited polysilicon layer and monocrystalline silicon substrate onI-Vcharacteristics of polysilicon emitter transistors are investigated. It is found that the position of this interfacial layer relative to the emitter-base junction has a crucial influence on the device characteristics. The observed highly nonlinear behavior of the Gummel plot is shown to result from the lacking of the monocrystalline emitter in the substrate. An interface model with trap-assisted tunneling is used to simulate device characteristics and qualitatively good agreement with experiments is achieved. A physical explanation is further given to such nonlinearity and a new regime of negative differential resistance in the IBversus VBEcurve is predicted based on computer simulation.     

Generalized theory and realization of a voltage-controlled negative resistance MOS device (lambda MOSFET)

A generalized theoretical approach used to predict circuits which exhibit the three-terminal negative resistance MOS characteristic is presented. The main structure of the positive feedback circuit is accomplished by connecting the drain and gate terminals of an n-channel enhancement mode MOSFET with the input and output terminals of an inverter circuit. The characteristic parameters such as the peak current, the peak voltage, the negative resistance, and the valley voltage are derived in a generalized form. Based on the theoretical predictions, several high density integrated circuits that give rise to a voltage-controlled negative resistance characteristic were fabricated and are described.     

A new trench base-shielded bipolar transistor

In this paper, a new power bipolar transistor structure called the trench base-shielded bipolar transistor (TBSBT) Is proposed and experimentally demonstrated. This structure incorporates deep p⁺ poly-Si trenches into the base of a conventional bipolar transistor. With the base shielded effectively by the p⁺ trenches, the base of the TBSBT can be made very narrow to achieve high current gain h_FE and high cut-off frequency f_T without compromising on the breakdown voltage. Experimental results show that the on-state anti switching characteristics of the TBSBT are significantly better than those of the existing power bipolar transistors     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

The transient integral charge control relation—A novel formulation of the currents in a bipolar transistor

The present paper describes the transient integral charge control (TICC) relation. This term designates a formula describing the emitter, base, and collector terminal currents of a bipolar junction transistor (BJT) for a one-dimensional current flow. The relation holds for dc as well as for transient bias conditions, and basically can be regarded as a more general formulation of Gummel's charge control relation [1], whose validity is restricted to dc conditions and to situations where recombination and generation effects are negligible. The structure of the TICC relation resembles Gummel's formulation extended by some additional terms. We shall use this relation in order to derive a formula for the high-frequency behavior of the transconductance. The expression obtained via the TICC relation allows for physical interpretation and simple calculation. The validity of the derived formulas is carefully checked by numerical means. This yields a validity range of our approach far beyond the Start of the high-current regime.     

Simulating power electronic systems—A new approach

The time-varying topology created by the switch-mode operation of power semiconductor devices in energy conversion systems presents difficulties in analysis. Presently available methods for simulating the behavior of these systems include the use of the digital computer, the conventional analog computer, and the breadboard. A new philosophically distinct technique called "parity simulation" produces a topologically isomorphic transformation of the system under study; that is, it exhibits a 1:1 correspondence, or parity, with the structure of the actual network. A parity simulator utilizes terminal equivalent representations of network elements. The microcomputer based interface is highly user oriented. Nonlinear or time-varying element parameters are easily incorporated. Several simulation examples are presented.