On the FinFET extension implant energy

The need of an ultrashallow junction technology for the extension of p-FinFETs has been investigated by integrated process and device simulations. For devices with 60 nm physical gate length, whose extensions are activated in a low thermal-budget process (spike anneal), it is found that the I/sub off/-I/sub on/ performance is invariant with respect to the extension implant energy. Nevertheless, the short-channel behavior worsens. This can be remedied by adding spacers to both sides of the gate before the extension implant, resulting in virtually identical dc characteristics and speed. Devices with gate lengths of 18 nm and below require dopant activation with negligible diffusion. Under those circumstances the short channel behavior of the FinFET is limited by the lateral straggle of the ion implant. Spacers may remedy what is otherwise poor short channel behavior due to a relatively high energy extension implant. However, this comes at the price of drastically worse drive current at a fixed off-current.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Crossed-film cryotron switching speed

To date there have been no direct measurements of the switching speed of an individual crossed-film cryotron (CFC) due to the extremely low gate resistance of the device in its normal state. A method which is, in principle, similar to conventional sampling techniques is used to determine the CFC switching speed with a 2-ns time resolution and a gate resistance sensitivity of 0.1 μΩ. CFC switching speeds are determined as a function of control current overdrive and gate current. In this way, the gain-bandwidth limitations of the device are experimentally determined. These data can be used to determine the optimum speeds of CFC logic circuits.     

Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND (OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area     

A novel fabrication method for the nanoscale tunneling field effect transistor

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.     

Field-induced interband tunneling effect transistor (FITET) with negative-differential transconductance and negative-differential conductance

The fabricated quantum-tunneling devices have a structure totally compatible with silicon-on-insulator CMOS device except for degenerate channel doping and the intentional omission of lightly doped drain (LDD) region. The key principle of the device operation is the field-induced interband tunneling effect, and thus the name of this quantum-tunneling device: FITET. In the transfer I-V characteristics of FITET, negative-differential transconductance (NDT) characteristics have been observed at room temperature. By controlling the critical device parameters to enhance field-effect such as gate oxide thickness, the peak-to-valley current ratio over 5 has been obtained at room temperature, and the negative-differential conductance (NDC) characteristics as well as NDT have been observed in the output I-V curves of the same FITET.     

铋掺杂对SrTiO3薄膜微观结构及阻变行为的影响

采用溶胶-凝胶及快速退火工艺在p+-Si上制备了Bi掺杂SrTiO_3薄膜,构建了Ag/Sr_(1-x)Bi_xTiO_3/p+-Si结构阻变器件,研究了Bi掺杂量对薄膜微观结构、器件阻变行为及特性的影响。结果表明:Bi掺杂量较低时并未改变Sr_(1-x)Bi_xTiO_3薄膜的相结构,但随着掺杂比例的增大,晶粒尺寸也明显增大,当掺杂量x=0.16时,有Bi4SrTi4O15及TiO2相形成;不同Bi掺杂量的Ag/Sr_(1-x)Bi_xTiO_3/p+-Si器件均呈现出双极性阻变特性,且有明显的多级阻变行为。随Bi掺杂量的增加,器件的阻变性能逐步提高,当x=0.12时器件的高、低阻态电阻比值最大,达到105左右,并且在2 000次可逆循环测试下,高、低阻态电阻比未出现衰减,表现出良好的抗疲劳特性,但当掺杂量x达到或超过0.16后,器件的性能呈下降趋势。Bi掺杂量的增大会导致器件高阻态时的导电机制从空间电荷效应(SCLC)导电机制(x0.16)转变为肖特基势垒发射(x=0.16)。器件在低阻态下均遵循欧姆导电机制。     

Enhanced Charge Injection Properties of Organic Field‐Effect Transistor by Molecular Implantation Doping

Organic semiconductors (OSCs) have been widely studied due to their merits such as mechanical flexibility, solution processability, and large‐area fabrication. However, OSC devices still have to overcome contact resistance issues for better performances. Because of the Schottky contact at the metal–OSC interfaces, a non‐ideal transfer curve feature often appears in the low‐drain voltage region. To improve the contact properties of OSCs, there have been several methods reported, including interface treatment by self‐assembled monolayers and introducing charge injection layers. Here, a selective contact doping of 2,3,5,6‐tetrafluoro‐7,7,8,8‐tetracyanoquinodimethane (F₄‐TCNQ) by solid‐state diffusion in poly(2,5‐bis(3‐hexadecylthiophen‐2‐yl)thieno[3,2‐b]thiophene) (PBTTT) to enhance carrier injection in bottom‐gate PBTTT organic field‐effect transistors (OFETs) is demonstrated. Furthermore, the effect of post‐doping treatment on diffusion of F₄‐TCNQ molecules in order to improve the device stability is investigated. In addition, the application of the doping technique to the low‐voltage operation of PBTTT OFETs with high‐k gate dielectrics demonstrated a potential for designing scalable and low‐power organic devices by utilizing doping of conjugated polymers.     

Local electrical characteristics of dielectrophoretically deposited carbon nanotubes

Electrostatic force microscopy and scanning gate microscopy are employed to investigate the local electrical characteristics of single-walled carbon nanotube (SWCNT) devices that are fabricated by alternating current dielectrophoresis with high spatial resolutions. The results show good electrical anchoring of nanotubes to electrodes and absence of local gate dependence as well as global gate dependence while device resistance can be dominated by contact resistances among bundles of SWCNTs.     

Impact of random dopant fluctuation effect on surrounding gate MOSFETs: from atomic level simulation to circuit performance evaluation

This paper investigates the impact of random dopant fluctuation effect on surrounding gate MOSFET, from atomic statistical simulation of device to circuit performance evaluation. The doping profile is generated by an analysis of each lattice atom and then the threshold voltage variation is obtained by device Drift-Diffusion simulation. Then the circuit performance evaluation is performed by feeding the result into a surrounding-gate MOSFET model. It is shown that a significant fluctuation in threshold voltage is due to the decreasing volume. The circuit simulation results also reveal that a surrounding gate MOSFET based 6-T SRAM presents a promising resistibility to noise disturbance.     

High mobility top-gated poly(3-hexylthiophene) field-effect transistors with high work-function Pt electrodes

We report high-performance top-gated organic field-effect transistors (OFETs) with regio-regular poly(3-hexylthiophene) (rr-P3HT). The high charge carrier mobility in rr-P3HT FETs (0.4 cm²/Vs) was achieved due to the relatively low contact resistance and high crystallinity of rr-P3HT films. The contact resistance was controlled mainly through the use of high work-function platinum (Pt) (5.6 eV) for the charge injection electrode and a top-gate, bottom-contact geometry that enabled an enhanced current injection via current crowding in the staggered device structure. Moreover, the top-gate configuration provided improved device stability in air ambient conditions via the presence of a gate dielectric and gate electrode on top of the organic semiconductor.     

DFT Modeling of Bulk-Modulated Carbon Nanotube Field-Effect Transistors

We report density-functional theory (DFT) atomistic simulations of the nonequilibrium transport properties of carbon nanotube (CNT) field-effect transistors (FETs). Results have been obtained within a self-consistent approach based on the nonequilibrium Green's functions (NEGF) scheme. We show that, as the current modulation mechanism is based on the local screening properties of the nanotube channel, a completely new, negative quantum capacitance regime can be entered by the device. We show how a well-tempered device design can be accomplished in this regime by choosing suitable doping profiles and gate contact parameters. At the same time, we detail the fundamental physical mechanisms underlying the bulk-switching operation, including them in a very practical and accurate model, whose parameters can be easily controlled in order to improve the device performance. The dependence of the nanotube screening properties on the temperature is finally explained by means of a self-consistent temperature analysis     

Tunable SnSe2/WSe2 Heterostructure Tunneling Field Effect Transistor

The burgeoning 2D semiconductors can maintain excellent device electrostatics with an ultranarrow channel length and can realize tunneling by electrostatic gating to avoid deprivation of band‐edge sharpness resulting from chemical doping, which make them perfect candidates for tunneling field effect transistors. Here this study presents SnSe₂/WSe₂ van der Waals heterostructures with SnSe₂ as the p‐layer and WSe₂ as the n‐layer. The energy band alignment changes from a staggered gap band offset (type‐II) to a broken gap (type‐III) when changing the negative back‐gate voltage to positive, resulting in the device operating as a rectifier diode (rectification ratio ~10⁴) or an n‐type tunneling field effect transistor, respectively. A steep average subthreshold swing of 80 mV dec^?1 for exceeding two decades of drain current with a minimum of 37 mV dec^?1 at room temperature is observed, and an evident trend toward negative differential resistance is also accomplished for the tunneling field effect transistor due to the high gate efficiency of 0.36 for single gate devices. The I _ON/I _OFF ratio of the transfer characteristics is >10⁶, accompanying a high ON current >10^?5 A. This work presents original phenomena of multilayer 2D van der Waals heterostructures which can be applied to low‐power consumption devices.     

Quality assessment of graphene: Continuity,uniformity, and accuracy of mobility measurements

With the increasing availability of large-area graphene,the ability to rapidly and accurately assess the quality of the electrical properties has become critically important.For practical applications,spatial variability in carrier density and carrier mobility must be controlled and minimized.We present a simple framework for assessing the quality and homogeneity of large-area graphene devices.The field effect in both exfoliated graphene devices encapsulated in hexagonal boron nitride and chemical vapor-deposited (CVD) devices was measured in dual current-voltage configurations and used to derive a single,gate-dependent effective shape factor,β,for each device.β is a sensitive indicator of spatial homogeneity that can be obtained from samples of arbitrary shape.All 50 devices investigated in this study show a variation (up to tenfold) inβ as a function of the gate bias.Finite element simulations suggest that spatial doping inhomogeneity,rather than mobility inhomogeneity,is the primary cause of the gate dependence ofβ,and that measurable variations ofβ can be caused by doping variations as small as 1010 cm-2.Our results suggest that local variations in the position of the Dirac point alter the current flow and thus the effective sample shape as a function of the gate bias.We also found that such variations lead to systematic errors in carrier mobility calculations,which can be revealed by inspecting the correspondingβ factor.     

Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Magnetoresistive amplifiers with superconductive elements

The construction and properties of certain superconductive amplifiers in which the resistance of a gate element is controlled by the electromagnetic field of a signal coil are described in this paper. Vacuum-deposited films of tin, which have narrow resistive transition widths, have been used as the gate elements, and the field has been applied perpendicularly to the film surface. The parameters of small-signal analysis are determined, and the influence of temperature, bias magnetic field, and zero-signal gate current upon power gains are shown. The limitations and merits of the device in its present form are discussed.     

Graphene–Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating‐gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH₃⁺), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al₂O₃ blocking dielectric layers. Important design rules are proposed for a high‐performance graphene memory device: i) precise doping of the graphene channel, and ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor‐type memory device. Additionally, the positively charged GO (GO–NH₃⁺) interacts electrostatically with hydroxyl groups of both UV‐treated Al₂O₃ and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene–graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10⁵ s), and good mechanical stability (1000 cycles).     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Influence of gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors

In this article, the significant effect of a thin gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors (DCFETs) is first demonstrated. When compared to the conventional InGaP/InGaAs DCFET, the device with the gate thermal oxide layer exhibits a higher gate turn-on voltage and nearly voltage-independent transconductances as the gate-to-source is biased form −0.75 V to 0 V, while the maximum transconductance is lower. Experimentally, the transconductance within 90% of its maximum value for gate voltage swing is 1.63 V in the gate-oxide device, which is greater than that of 1.35 V in the device without the gate thermal oxide layer. Furthermore, it maintains a high drain current level at negative gate bias in the gate-oxide device, which can be attributed that the thermal oxide layer with a considerably large energy gap absorbs more of gate negative voltage and the influence of negative voltage on the gate depleted thickness is relatively slight.     

Quantum Simulation of Device Characteristics of Silicon Nanowire FETs

A quantum simulation of silicon nanowire field-effect transistors has been performed in the frame work of the effective mass theory, where the three-dimensional Poisson equation was solved self-consistently with the mode-space nonequilibrium Green's function equations in the ballistic transport regime. The dependence of the device performance on the gate length and width for three types of gate configuration has been studied, focusing on the contribution of the tunneling current to the total current. The effects of gate underlap and the corner rounding of silicon body on the device performance have been also investigated quantitatively, leading to the conclusions that the gate underlap is an important factor in improving the subthreshold characteristics of the device, but the corner rounding of silicon body is not a significant factor, especially for devices with silicon body width of a few nanometers