Analytical modeling and parameter extraction of top and bottom contact structures of organic thin film transistors

This paper proposes a structure based model of an organic thin film transistor (OTFT) and analyzes its device physics. The analytical model is developed for the top contact structure by mapping the overlap region to the resistance (in the vertical direction) that includes the contact and the bulk sheet resistances. Total device resistance includes the vertical resistance per unit area of the contact region and the sheet resistance of the channel. In addition, the drain and the gate voltages take into account the potential drop across the respective contacts. The gate bias dependent mobility is considered in place of constant mobility, since; it is more realistic and relevant to the organic TFTs. The proposed analytical model is also applied to the bottom contact structure and the current–voltage (I–V) characteristics are obtained. Furthermore, a differential method is employed to extract the parameters, such as, mobility enhancement factor γ, threshold voltage V_T, mobility µ_B, characteristic length L_C, vertical resistance R_V and contact resistance R_C. Finally, the model is validated in terms of electrical characteristics and performance parameters for both top and bottom contact structures. The analytical model results are in close agreement with the experimental results.     

Direct writing of inkjet-printed short channel organic thin film transistors

A direct-writing fabrication process for fully inkjet-printed short-channel organic thin-film transistors (OTFTs) has been developed. Channels as narrow as 800 nm between two printed Ag electrodes were achieved by printing a special Ag ink on an SU-8 interlayer, which can be partially dissolved by the solvents used in the Ag ink. The ridge formed along the printed Ag line edges due to redistribution of the interlayer material during the drying process limits the ink spread, and separates neighboring printed lines, and is the key to defining an ultra-narrow channel for transistor fabrication. The short-channel OTFTs fabricated using this technique have demonstrated well-defined linear and saturation regimes. An extracted mobility of 0.27 cm²/Vs with an on/off ratio of 10⁵ was obtained at a driving voltage of −12 V. The excellent performance of these devices demonstrates the potential of this technique in fabrication of short-channel devices using standard printing technologies.     

Characterization of organic thin film transistors with hysteresis and contact effects

We propose two procedures to extract information about the trapping processes that occur in organic thin film transistors (OTFTs) that exhibit both contact and hysteresis effects. In particular, the variation of trapped charge during hysteresis cycles is determined by the separate analysis of current–voltage curves for the intrinsic transistor and for the contact region. The extraction of these curves is done with the help of our previous compact model that reproduces the current–voltage characteristics of OTFTs with contact effects. The model is used to fit experimental output characteristics with hysteresis and to extract the parameters of the model, such as the mobility and the threshold voltage. The variation of the threshold voltage with trapped charges during voltage cycling and using existing transistor models results in different sets of parameters needed to reproduce the experimental data. However, not all these parameters have proper physical meanings. In order to find a unique physical solution, the current–voltage curves of the contacts and current–voltage curves of the intrinsic transistor, extracted from the output characteristics measured at the transistor terminals, are separately analyzed. The study of the evolution with the gate voltage of the free-charge density in the contact allows for finding this unique solution. The results of this method are compared with published results that use more elaborate experimental techniques, such as the four-terminal method or transient experiments.     

An analysis of the difference in behavior of top and bottom contact organic thin film transistors using device simulation

This paper presents a systematic analysis of an already reported phenomenon, namely, the difference in device performance of top and bottom contact organic thin film transistors (OTFT) by combining experiments and two-dimensional device simulations. The mobility of the as measured devices in the bottom contact OTFT is found to be lower by two orders of magnitude than the top contact structure, which is generally attributed to the higher metal-semiconductor contact resistance in the bottom contact devices due to lower contact area. However, we found that this large mobility difference exists even after correcting for the metal-semiconductor contact resistance through transfer line method (TLM). This result suggests that structural differences are playing a dominant role in lowering down the performance of bottom contact devices. This effect is then systematically investigated through two-dimensional physics-based numerical simulations by considering several structural inhomogenities around the contacts. The main reason for such an occurrence is attributed to the poor morphology (or comparatively low mobility) of pentacene films around the source/drain electrodes in the bottom contact devices. Finally, we also show a reasonable match between the simulated and experimental device characteristics, enabling calibration of the simulator for further use in design of OTFTs.     

Simultaneous extraction of source and drain resistances in top contact organic thin film transistors from a single test structure

A method of extraction of source and drain resistances in linear mode of operation from a single transistor is described. The proposed method can also be used to measure source resistance over the entire operating range from linear to saturation mode of operation. The method uses two floating probes outside the channel, one adjacent to the source and the other to the drain to sense the voltage under these contacts. Using transmission line analysis, the source and drain resistances are directly extracted from these measurements. 2D numerical simulation results confirm the validity of the proposed technique and sensitivity analysis shows that the method is more accurate than the conventional gated four probe technique, especially, when the source resistance is much smaller than the channel resistance. Experimental results obtained with Pentacene top-contact transistors are used to illustrate the proposed technique. Analysis of two devices with very different source resistance is carried out to highlight the ability of the proposed technique to offer insight into the different contributing factors. Current crowding under the source contact and accurate estimation of mobility without the distorting effects of source resistance are also described.     

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φ_b = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10⁵ V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |V_ds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V_ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |V_ds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.     

Gate-planarized organic polymer thin film transistors

We report in this paper the fabrication and characterization of a new gate-planarized organic polymer thin-film transistor (GP OP-TFT). We describe in detail the effects of the measurement procedure on the GP OP-TFT electrical characteristics and extracted parameters and show that it is extremely critical to carefully control the electrical measurement conditions to obtain accurate and meaningful results, before any material optimization is undertaken. We also describe the importance of normalization of electrical characteristics and extracted parameters for a proper comparison of different devices. Finally, we report and analyze the gate voltage and channel length dependence of the TFT field-effect mobility.     

高性能钆铝锌氧薄膜晶体管的制备

本文研究并制备了钆铝锌氧薄膜和以钆铝锌氧为有源层的薄膜晶体管。钆铝锌氧薄膜材料的光致发光光谱和透过率说明钆铝锌氧薄膜在透明显示方向的应用潜力。透射电子显微镜揭示了钆铝锌氧薄膜的非晶态微观结构。钆铝锌氧薄膜晶体管显示了良好的转移特性和输出特性。器件开关比大于10~5、饱和迁移率约为10cm~2·V~(-1)·s~(-1)。实验结果表明,钆铝锌氧薄膜可用作氧化物薄膜晶体管的有源层材料;钆铝锌氧薄膜晶体管可作为像素电路的驱动器件。     

Fabrication of organic thin film transistors on Polyethylene Terephthalate (PET) fabric substrates

In this paper organic thin film transistors (OTFTs) are directly fabricated on fabric substrates consisting of Polyethylene Terephthalate (PET) fibers. A key process is coating the polymer layers on the fabric in order to reduce the large surface roughness of the fabric substrate. Two polymers, i.e. polyurethane (PU) and photo-acryl (PA), are used to reduce the large surface roughness and simultaneously improve the process compatibility of the layers with the subsequent OTFTs processes while also retaining the original flexibility of the fabric. The surface roughness of the PU/PA-coated fabric is significantly reduced to 0.3 μm. Furthermore, the original flexibility of the PET fabric remained after coating of the PU/PA polymer layers. The mobility of the OTFTs fabricated on the PU-PA coated fabric substrate is 0.05 ± 0.02 cm²/V s when three PA layers and 90 nm thick pentacene layer were used. The performance does not vary even after 30,000 bending test.     

Enhanced channel mobility in polysilicon thin film transistors

Due to scattering by charged grain boundaries, carrier mobility μ in the channel of polysilicon thin film transistors (TFT) is usually much lower than the bulk silicon value. We have studied a series of _p-channel TFT devices with varying gate oxide thicknesses d_ox and found that CL shows a strong increase when d_ox is reduced below 150 Å. We attribute this effect to the screening of the charged grain boundary by the gate conductor. The screening becomes effective when the characteristic length associated with the potential barrier at charged grain boundaries becomes comparable to the optical distance between the grain boundary charge and its mirror image in the gate electrode. From the known structure parameters the onset of the strong screening is estimated to occur at oxide thicknesses of about 100 Å     

Fabrication of Au/PEDOT stacked electrodes for organic thin film transistors by imprinting technology

In this work, the Au/PEDOT stacked source/drain electrodes of OTFTs were fabricated by combining the micro-contact inking and reversal imprinting. The PEDOT was inked on the mold by the micro-contact process and the Au/PEDOT stacked layer was transferred on pentacene by imprinting technology. The threshold voltage, and on-off ratio, carrier mobility, and source/drain contact resistance of organic TFTs were all improved by the proposed process.     

Impact of Source and Drain Contact Thickness on Performance of Organic Thin film Transistors

This paper analyzes the impact of source(ts) and drain(td) contact thicknesses on top contact(TC) and bottom contact(BC) organic thin film transistors(OTFTs) with a gate in the bottom, using a benchmarked industry standard Atlas 2-D numerical device simulator. The parameters including drive current(Ids), mobility(μ), threshold voltage(Vt)and current on-off ratio(ION/IOFF) are analyzed from the device physics point of view on different electrode thicknesses, ranging from infinitesimal to 50 nm, for both top and bottom contact structures. Observations demonstrate that the performance of the BC structure is more affected by scaling of ts=din comparison to its counterpart. In the linear region, the mobility is almost constant at all the values of ts=dfor both structures. However,an increment of 18% and 83% in saturation region mobility is found for TC and BC structures, respectively with scaling down ts=dfrom 50–0 nm. Besides this, the current on-off ratio increases more sharply in the BC structure.This analysis simplifies a number of issues related to the design and fabrication of organic material based devices and circuits.     

Modeling the gate bias dependence of contact resistance in staggered polycrystalline organic thin film transistors

We have modeled the dependence on the gate voltage of the bulk contact resistance and interface contact resistance in staggered polycrystalline organic thin film transistors. In the specific, we have investigated how traps, at the grain boundaries of an organic semiconductor thin film layer placed between the metal electrode and the active layer, can contribute to the bulk contact resistance. In order to the take into account this contribution, within the frame of the grain boundary trapping model (GBTM), a model of the energy barrier E_B, which emerges between the accumulation layer at the organic semiconductor/insulator interface and injecting contact, has been proposed. Moreover, the lowering of the energy barrier at the contacts interface region has been included by considering the influence of the electric field generated by the accumulation layer on the injection of carriers at the source and on the collection of charges from the accumulation layer to the drain contact. This work outlines both a Schottky barrier lowering, determined by the accumulation layer opposite the source electrode, as well as a Poole-Frenkel mechanism determined by the electric field of the accumulation layer active at the drain contact region. Finally it is provided and tested an analytical equation of our model for the contact resistance, summarizing the Poole-Frenkel and Schottky barrier lowering contribution with the grain boundary trapping model.     

Optimization of electrohydrodynamic-printed organic electrodes for bottom-contact organic thin film transistors

In this study, we investigate the optimization of printed (3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) as source/drain electrodes for organic thin film transistors (OTFTs) through electrohydrodynamic (EHD) printing process. The EHD-printed PEDOT:PSS electrodes should fulfill the prerequisites of not only high conductivity but also optimum surface tension for successful jetting. The conductivity of PEDOT:PSS was dramatically enhanced from 0.07 to 352 S/cm by the addition of dimethylsulfoxide (DMSO). To use the DMSO-treated PEDOT:PSS solution in the EHD printing process, its surface tension was optimized by the addition of surfactant (Triton X-100), which was found to enable various jetting modes. In the stable cone-jet mode, the patterning of the modified PEDOT:PSS solution was realized on the surface-functionalized SiO₂ substrates; the printed line widths were in the range 384 to 81 μm with a line resistance of 8.3 × 10³ Ω/mm. In addition, pentacene-based OTFTs employing the EHD-printed PEDOT:PSS as source and drain electrodes were found to exhibit electrical performances superior to an equivalent vacuum-deposited Au-based device.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Optimization of nanocomposite gate insulators for organic thin film transistors

Nanocomposite gate insulators consisting of (Ba, Sr)TiO₃ (barium strontium titanate; BST) nanoparticles and crosslinked poly(4-vinyl phenol) (PVP) polymers were fabricated. Well-dispersed nanocomposite films were prepared by optimizing the BST nanoparticle size sorting process (ultrasound crushing and centrifuge method). The size-sorted BST nanoparticles (∼30 nm in size) were homogeneously mixed in the PVP host polymer in various BST contents, from 0 to 70 wt%, to tune the dielectric constant (κ) of the resulting nanocomposite films. The composite films exhibit three-fold increase in the κ value from 3.9 to 11.3. The physical properties including leakage current and surface roughness of the composites were also measured as a function of the BST loading content and particle dispersion. The relationship between these properties and the electrical performance of the corresponding organic thin film transistor were explored.     

Laser printing of air-stable high performing organic thin film transistors

Active layers involved in top contact organic thin film transistors (TC-OTFTs) have been printed using the laser induced forward transfer (LIFT) technique. Bis(2-phenylethynyl) end-substituted terthiophene (diPhAc-3T) as a p-type organic semiconductor was vacuum evaporated on a quartz substrate prior to the transfer by laser onto an acceptor substrate to form an organic active layer for charge transport. The resulting printed diPhAc-3T pixels on the receiver substrates have a homogeneous morphology as shown by optical microscopy and atomic force microscopy (AFM). Electrical characterizations demonstrated that these transistors are fully functional with hole mobilities up to 0.04 cm²/V s, threshold voltage V_t near 0 V and I_on/I_off ratio up to 2.8 × 10⁵. The efficient cohesion of diPhAc-3T vacuum evaporated thin films induced by 3-dimensional growth offers an exceptionally high physical resistance to laser pulses. The large intermolecular interaction involved in such growth mechanism makes the thin films less sensitive to the mechanical damages induced by the laser. Due to the optical properties of diPhAc-3T, the use of a protecting layer deposited on the donor substrate prior to the diPhAc-3T active layer to trap the incident radiation during the LIFT was not required.     

Residue-free room temperature UV-nanoimprinting of submicron organic thin film transistors

In this study we report on an innovative nanoimprint process for the fabrication of entirely patterned submicron OTFTs in a bottom-gate configuration. The method is based on UV-Nanoimprint Lithography (UV-NIL) combined with a novel imprint resist whose outstanding chemical and physical properties are responsible for the excellent results in structure transfer. In combination with a pretreated stamp the UV-curable resist enables residue-free imprinting thus making etching obsolete. A subsequent lift-off can be done with water. The UV-NIL process implies no extra temperature budget, is time saving due to short curing times, eco-friendly due to a water-based lift-off, simple because it is etch-free and completely r2r compatible. It works perfectly even if ultra-thin organic and hybrid films are used as gate dielectrics. On this basis entirely patterned functional submicron OTFTs with pentacene as the semiconductor are fabricated showing clear saturation, low switch-on voltage (～3 V) and a sufficiently high on–off ratio (10³).     

Contact effects in organic thin film transistors with printed electrodes

The influence of contact effects on the performance of pentacene thin film transistors with printed electrodes was investigated. The electrodes of the transistor were realized by a combination of microcontact printing and selective dewetting/wetting. Printing of silane based self-assembled monolayers on glass or silicon substrates allows for the modulation of the surface energy, so that polymers or resists can be selectively deposited in the hydrophilic regions of the substrate, whereas the hydrophobic regions stay uncoated. A poly methyl methacrylate (PMMA) resist was selectively deposited in the hydrophilic regions. The resists structures were used as a template to pattern electrodes of pentacene thin film transistors by a lift-off process. The transistors exhibit charge carrier mobilities of 0.2 cm²/V s, low threshold voltages, and high on/off ratios of 10⁶. The pentacene transistors with printed drain and source electrodes were compared to devices patterned by optical lithography. In particular the influence of the drain and source contacts on the charge carrier mobility of the devices will be discussed. A simple model will be presented which takes the influence of contact effects into account when describing the electrical behavior of the transistors.     

Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (α-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an α-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.