Surface damage in wire-cut silicon wafers

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Grinding of silicon wafers using an ultrafine diamond wheel of a hybrid bond material

An ultrafine diamond wheel of a mesh size of 12,000 was fabricated by using a hybrid bond material, which consists of silicon carbide, silica and alumina. The employment of the newly developed wheel enabled excellent performance during grinding of silicon wafers. An extremely smooth surface of an average roughness of 0.6 nm was achieved. TEM examinations showed that the total thickness of the defected layer was less than 60 nm.     

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.     

Damage mechanisms during lapping and mechanical polishing CdZnTe wafers

CdZnTe wafers were machined by lapping and mechanical polishing processes, and their surface and subsurface damages were investigated.The surface damages are mainly induced by three-body abrasive wear and embedded abrasive wear during lapping process. A new damage type, which is induced by the indentation of embedded abrasives, is found in the subsurface. When a floss pad is used to replace the lapping plate during machining, the surface damage is mainly induced by two-body abrasive and three-body abrasive wear, and the effect of embed-ded abrasives on the surface is greatly weakened. Moreover, this new damage type nearly disappears on the subsurface.     

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

The polishing mechanism of electrochemical mechanical polishing technology

In this paper, the polishing mechanism of the electrochemical mechanical polishing (ECMP) technology for tooling steel SKD11 was investigated. Suitable electrochemical process parameters were evaluated. The electrochemical characteristics of a material such as active, passive and trans-passive (dissolution) can be revealed from its I–V curve. The characteristics of passive and trans-passive have great effects on the ECMP polishing mechanism. Experimental procedures included qualitative, quantitative and surface quality analyses. Qualitative analyses utilized potentiostat to study the I–V curves of a specific specimen in various electrolytes and electrolytic concentrations, and to find out the voltages at each electrochemical state. In quantitative analyses, the electrochemical polishing processes of the ECMP technology were conducted. From the measured and theoretical weight losses, each process state can be verified whether or not it followed the Faraday’s law. Finally, the surface roughness was measured by a surface profiler. The scanning electron microscopy (SEM) was used to observe the surface profile. The energy dispersive spectroscopy (EDS) analysis was employed to analyze the metallurgical compositions of the surface. In summary, the proposed mechanism and analyses were a good methodology in finding suitable electrochemical process parameters for ECMP technology.     

A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.     

晶片材料的超精密加工技术现状

文章介绍了晶片材料的超精密加工设备以及几种典型晶片材料加工工艺的最新发展 ,综述了几种典型超精密加工设备的特点以及单晶硅片、石英晶体、K9玻璃、钽酸锂单晶材料的加工工艺方法 ,探讨了晶片材料的超精密加工技术的发展趋势。     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

铜化学机械抛光材料去除机理研究

本文根据铜CMP过程中表面材料的磨损行为,建立了铜CMP时的材料去除率构成成分模型,并通过材料去除率实验,得出了各机械、化学及其交互作用所引起的材料去除率及其作用率:当np=nw=200r/min时,有最佳材料去除率,此时单纯的机械作用率为9.2%;单纯的化学作用率为仅为2.1%,抛光垫的机械与化学交互作用率为5.08%;磨粒的机械与化学交互作用率为83.6%。通过对实验结果进行分析,可得如下结论:硅片化学机械抛光中,一定的参数下有一个最优的抛光速度;在最优的速度下,机械与化学之间交互作用达到平衡,这时可获得最高的材料去除率;硅片化学机械抛光过程是一个多变的动态过程,仅仅通过增加机械作用或化学作用不能获得理想的材料去除效果。本文的研究结果可为进一步研究硅片CMP时的材料去除机理提供理论参考依据。     

Fine grinding of silicon wafers: machine configurations for spindle angle adjustments

This paper addresses an important aspect of silicon wafer fine grinding: machine design. For any commercially available wafer grinders, spindle angle adjustments based on the wafer shape ground is almost inevitable in order to achieve flat wafers. However, there has been no commonly accepted guidance for the design of machine configurations to ensure the easiest adjustment. Practitioners doing spindle angle adjustments have been frustrated by the difficulties of achieving the adjustments on commercial wafer grinders. This paper first illustrates such difficulties with a machine configuration frequently cited in the literature. It then demonstrates the potential ease of spindle angle adjustments with a proposed machine configuration. Next, it shows mathematically that the proposed configuration (specifically, a pair of the axes for spindle angle adjustments) is uniquely determined once the wheel diameter and wafer diameter are known. It also shows that the proposed configuration is the best in terms of ease in spindle angle adjustments. The spindle angle adjustments will be more difficult with any other configurations deviating from the proposed one.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

A finite element analysis of temperature variation in silicon wafers during wiresaw slicing

Temperature variation during slicing can cause undesirable warp and nanotopography on wafer surfaces, especially for large wafers. In this paper, a finite element model is constructed and presented to analyze and synthesize temperature variation of ingot during wiresaw slicing. The heat flux and natural convection boundary condition arising during slicing have been studied and incorporated in the model as well as the material removal. The model is designed to accommodate time-dependent boundary conditions and geometry which are integral to wiresaw slicing process. The results obtained from the model compare very well with the experimental results available in the literature. A method is proposed in order to obtain a relatively flat profile of temperature during slicing in order to reduce warp due to heat generation by intelligent control of boundary conditions. The method is tested using the model developed. The proposed method can be utilized by practitioners in order to obtain wafers with less warp and improved nanotopography due to thermal aspects in slicing using wiresaws.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

A grinding-based manufacturing method for silicon wafers: an experimental investigation

The majority of semiconductors are built on silicon wafers. Future semiconductors will require flatter wafers with a lower price. The lapping-based manufacturing method currently used to manufacture silicon wafers will not be able to meet the ever-increasing demand cost-effectively. This paper reports an experimental investigation into a grinding-based manufacturing method, which has potential to manufacture flat silicon wafers at a lower cost. Background information on semiconductors and silicon wafers is presented first. After a discussion on drawbacks of the lapping-based method, the grinding-based method is described. Next, experimental results with the grinding-based method are presented and discussed. The results from this investigation have demonstrated the potential of the grinding-based method and revealed several directions for future work.     

Grinding induced subsurface cracks in silicon wafers

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. To ensure high surface quality, the damage layer generated by each of the machining processes (such as lapping and grinding) has to be removed by its subsequent processes. Therefore it is essential to assess the subsurface damage for each machining process. This paper presents the observation of subsurface cracks in silicon wafers machined by surface grinding process. Based on cross-sectional microscopy methods, several crack configurations are identified. Samples taken from different locations on the wafers are examined to investigate the effects of sample location on crack depth. The effects of grinding parameters such as feedrate and wheel rotational speed on the depth of subsurface crack have been studied by a set of factorial design experiments. Furthermore, the relation between the depth of subsurface crack and the wheel grit size is experimentally determined.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

CMP抛光半导体晶片中抛光液的研究

本文分析了化学机械抛光(CMP)半导体晶片过程中抛光液的重要作用,总结了抛光液的组成及其化学性能(氧化剂、磨料及pH值等)和物理性能(流速、粘性及温度)对抛光效果的影响规律,研究发现:酸性抛光液常用于抛光金属材料,pH最优值为4,碱性抛光液常用于抛光非金属材料,pH最优值为10～11.5;氧化剂能有效提高金属材料的抛光效率和表面平整度;磨料的种类、浓度及尺寸会影响抛光效果;分散剂有助于保持抛光液的稳定性;抛光初始阶段宜采用较低流速,然后逐渐提高;抛光液的粘性会影响晶片与抛光垫之间的接触模式、抛光液的均布、流动及加工表面的化学反应;抛光液温度的升高有助于提高抛光效率.最后本文指出了抛光液循环使用的重要意义及常用方法.     

硅片化学机械抛光技术的研究进展

随着硅片厚度的增大和芯片厚度的减小,硅片在加工中的材料去除量增大,如何提高其加工效率就成了研究的热点之一。由于化学机械抛光过程复杂,抛光后硅片的质量受到多种因素的影响,主要包括抛光设备的技术参数、耗材(抛光垫和抛光液)的性质和硅片自身在抛光时的接触应力状态等。本文介绍了硅片化学机械抛光技术的研究进展,讨论了影响硅片抛光后表面质量和表面材料去除率的因素,如抛光液、抛光垫、抛光压力等,并对目前用于硅片化学机械抛光的先进设备进行了综述。