Architecture of field-programmable gate arrays

A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed     

The yield enhancement of field-programmable gate arrays

The fine granularity and reconfigurable nature of field-programmable gate arrays (FPGA's) suggest that defect-tolerant methods can be readily applied to these devices in order to increase their maximum economic sizes, through increased yield. This paper identifies the inability to contain faults within single cells and the need for fast reconfiguration as the key obstacles to obtaining a significant increase in yield. Monte Carlo defect modeling of the photolithographic layers of VLSI FPGA's is used as a foundation for the yield modeling of various defect-tolerant architectures. Results suggest that a medium-grain architecture is the best solution, offering a substantial increase in size without significant side effects. This architecture is shown to produce greater gate densities than the alternative approach of realizing ultralarge scale FPGA's-multichip modules     

Architecture of field-programmable gate arrays: the effect of logicblock functionality on area efficiency

The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block     

Fast block implementation of two-dimensional FIR digital filters by systolic arrays

A systolic block implementation is described of two-dimensional (2D) FIR and quarter-plane digital filters. Initially, a general 2D block realization model is presented, which does not assume any restricted relation with respect to the block lengths. A high degree of concurrency is achieved by exploiting the pipelining of the array processors in conjunction with the inherent parallelism of the block realization structures. The resulting systolic implementation is characterized by a high degree of modularity, regularity, repetitiveness and local communications and permits very high sampling rates. The increase of the block lengths of the implementation is analogous to the attained throughput rate, with respect to the cost of supporting hardware. The proposed systolic implementation is suitable for real-time image processing applications.     

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.     

An architecture for a DSP field-programmable gate array

This paper describes an application specific architecture for field-programmable gate arrays (FPGAs). Emphasis is placed on the logic module architecture and channel segmentation for the FPGAs targeted for application areas related to digital signal processing (DSP). The proposed logic module architecture is well-suited for efficient implementation of frequently used logic functions in the DSP application area. This is mainly because it is possible to implement most of these functions using one logic module, which results in a reduction in both the net lengths and the number of antifuses used. The performance improvements are achieved by customizing the logic module architecture and the programmable interconnect to suit the requirements of DSP applications     

B-spline FIR filters

This paper presents an efficient procedure for the design of interpolated FIR (IFIR) filters with linear phase. The algorithm uses the uniform B-spline function as an interpolator and solves the optimal Chebyshev approximation problem on the optimal subinterval. The technique can be used for the design of general lowpass, highpass and bandpass filters. While the number of multiplications of the IFIR filter is dependent on the bandwidth and the center frequency of the desired filter, it provides the minimum number of multiplications achievable and nearly always provides a substantial reduction when compared to Parks-McClellan designs.     

GANGLION-a fast field-programmable gate array implementation of aconnectionist classifier

71 The architecture, implementation, and application of GANGLION, a totally digital connectionist classifier, are described. This fully interconnected feedforward net with one hidden layer is capable of generating 4.48 billion interconnection/s. The architecture is realized on a single 9U VME card and is built entirely from off-the-shelf components. The very high throughput of 20 million decision/s is achieved by making efficient use of field-programmable gate arrays. Specifically, the authors take advantage of the reprogrammability of the devices to automatically generate new custom hardware for each application of the classifier     

Configurable analogue building blocks for field-programmable analogue arrays

In this article, the design of configurable analogue blocks for field programmable analogue arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. The realisation of these functions depends on differential continuous-time current-mode translinear loop techniques. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by modifying the block's biasing conditions digitally. Simulation results for the presented circuits are included.     

Hardware-efficient FIR filters with reduced adder step

A technique for reducing the hardware complexity of constant coefficient finite impulse response (FIR) digital filters, without increasing the number of adder steps in the multiplier block adders, is presented. The filter coefficients are adjusted so that the number of full adders in the hardware implementation of any coefficient is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a significant reduction in both the multiplier block adders and the multiplier block full adders when compared to existing techniques.     

Least-squares multirate FIR filters

The authors propose a new least-squares design procedure for multirate FIR filters with any desired shape of the (band-limited) frequency response. The aliasing, inherent in such systems, is implicitly taken into account in the approximation criterion     

On linear-phase FIR filters with variable bandwidth

Recently, a particular structure for linear-phase finite-impulse response (FIR) filters with a variable bandwidth has received attention. In this structure, the overall transfer function is a weighted linear combination of fixed subfilters, with the weights being directly determined by the bandwidth. An advantage of this structure is that there are only a few adjustable parameters (weights), which results in a simple updating routine. However, in this paper, it is demonstrated that the use of a number of fixed regular overdesigned filters, each taking care of a part of the frequency region, in fact results in a lower overall arithmetic complexity. The price to pay is an increased group and phase delay.     

Design of FIR filters with reduced computations

The performance of a symmetric nonrecursive filter can be improved by multiple use of the same filter. The method is based on an Amplitude Change Function (ACF). An approach to the design of nonrecursive filters using an ACF is discussed in this paper. The prototype filter chosen is a Recursive Running Sum (RRS) filter which does not require any multipliers for its implementation. The required filter specifications are met by multiple use of the RRS filters. The overall filter requires a much smaller number of multiplications and adders than the one designed using the conventional method. It is shown that this method provides reduced noise due to coefficient quantization and product quantization compared with the conventional design technique.     

User-programmable gate arrays

A very flexible gate array that speeds the job of designing, updating, or varying the logic circuitry that turns standard microprocessor and memory ICs into computers and peripheral equipment is examined. The gates on this kind of IC are interconnected under software control, and downloaded into local memory cells from a program written by the user, which can alter it almost at will. The array is manufactured with a grid of interconnections consisting of metal segments and programmable switching points. The user's program defines which switching points are on and which are off, and in this way groups and interconnects the gates into useful functions. On conventional gate-array ICs, the interconnections are made once and for all by the manufacturer using photolithographic masks. Various types of arrays and methods for programming them are described. The approach to designing them is discussed, highlighting differences from the process for factory-configured gate arrays. Some example applications are presented     

Two-dimensional FIR digital filters with maximally flat magnitude

Generation of a class of maximally flat magnitude two-dimensional FIR functions employing McClellan transformation is described and their properties are discussed.     

Computer-aided design of FIR filters

A computer-aided technique for designing FIR digital filters with close to linear phase property is presented. The approach is based on a constrained optimisation problem designed to minimise the mean-square error between a desired response and the filter response over a passband of interest subject to a mean-square stopband constraint. Numerical results are presented to illustrate the performance achievable.<>     

Interpolated narrowband lowpass FIR filters

The article describes a class of digital filters, called interpolated finite impulse response (IFIR) filters that can implement narrowband lowpass FIR filter designs with a significantly reduced computational workload relative to traditional FIR filters. Topics discussed include: optimum expansion factor choice, number of FIR filter taps estimation, IFIR filter performance modeling, passband ripple considerations, implementation, and filter design.     

Implementing division with field programmable gate arrays

This article presents a method to map digit-recurrence arithmetic algorithms to lookup-table based Field Programmable Gate Arrays (FPGAs). By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area. To illustrate this method, a radix-2 digit-recurrence division algorithm is mapped to the Xilinx XC4010, a lookup-table based FPGA. The mapping develops a linear sequential array design that avoids the common problem of large fanout delay in the critical path. This approach has a cycle time independent of precision while requiring approximately the same number of logic blocks as a conventional design.     

On fast FIR filters implemented as tail-canceling IIR filters

We have developed an algorithm based on synthetic division for deriving the transfer function that cancels the tail of a given arbitrary rational (IIR) transfer function after a desired number of time steps. Our method applies to transfer functions with repeated poles, whereas previous methods of tail-subtraction cannot. We use a parallel state-variable technique with periodic refreshing to induce finite memory in order to prevent accumulation of quantization error in cases where the given transfer function has unstable modes. We present two methods for designing linear-phase truncated IIR (TIIR) filters based on antiphase filters. We explore finite-register effects for unstable modes and provide bounds on the maximum TIIR filter length. In particular, we show that for unstable systems, the available dynamic range of the registers must be three times that of the data. Considerable computational savings over conventional FIR filters are attainable for a given specification of linear-phase filter. We provide examples of filter design. We show how to generate finite-length polynomial impulse responses using TIIR filters. We list some applications of TIIR filters, including uses in digital audio and an algorithm for efficiently implementing Kay's optimal high-resolution frequency estimator