FIR滤波器的DSP实现

介绍了FIR滤波器的基本结构及设计方法,结合实例,给定滤波器的数字指标。利用FDATool来确定FIR滤波器抽头系数。基于DSP平台,采用MATLB产生待滤波输入信号导入到用C语言实现的FIR低通滤波器中,并且在CCS上仿真,对仿真结果与理论值进行比较。波形仿真结果和理论值相吻和表明设计的系统是正确、稳定的。不同的应用场合,FIR滤波器要求有不同性能,只要修改本设计中滤波器的系数,就可以实现性能不同的FIR滤波器。     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described     

基于AltiVec的高效FIR滤波器优化设计

随着需求的发展,信号处理系统对实时性的要求越来越高,这就要求对涉及到的信号处理算法的运算时间有了严格的限制。本文介绍了一种在PowerPC平台上,基于AltiVec技术的FIR滤波器设计方法。仿真实验表明,此种FIR滤波器的实现方法运算速度快,实时性好,性能优于在传统DSP平台上的FIR滤波器设计方法。     

基于分布式算法的高阶FIR滤波器及其FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。     

FIR数字滤波器在DSP上的实现

在TMS320C54x系统开发环境CCS(Code Composer Studio)下对FIR滤波器的DSP实现原理进行了讨论。利用Matlab中的FIR数字滤波器的函数设计相应的滤波器,对得到的滤波器系数采用Q15格式表示,并用C语言产生模拟输入信号。将获取的系数和输入信号通过相应的指令调到DSP芯片的数据存储器中,运用MAC指令、循环缓冲寄存器、块循环寄存器实现已知混合信号的滤波。通过实验仿真,从输入信号和输出信号的时域和频域曲线可看出在DSP上实现的FIR滤波器能完成预定的滤波任务。     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.     

软件无线电信道处理的DSP实现

本文重点研究了软件无线电(Software Defined Radio,SDR)中不同信道的处理技术,其技术关键在于构建不同频段的数字滤波器进行不同信道信息的接收处理.在建立软件无线电信道模型的基础上,利用MATLAB实现了多阶FIR滤波器的设计,并将算法移植到DSP软件设计当中,在DSP的集成开发环境CCS下对FIR滤波进行了仿真,仿真结果达到了SDR的信道处理要求.     

Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic

Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of revolutionizing sectors of digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPGAs were considered to be only a rapid prototyping and low-volume production technology. FPGAs are now attempting to move into the mainstream DSP as their density and performance envelope steadily improve. While evidence now supports the claim that FPGAs can accelerate selected low-end DSP applications (e.g., FIR filter), the technology remains limited in its ability to realize high-end DSP solutions. This is due primarily to systemic weaknesses in FPGA-facilitated arithmetic processing. It will be shown that in such cases, the residue number system (RNS) can become an enabling technology for realizing embedded high-end FPGA-centric DSP solutions. This thesis is developed in the context of a demonstrated RNS/FPGA synergy and the application of the new technology to communication signal processing.     

基于Matlab的FIR滤波器在DSP中的实现

本文主要对基于Matlab的FIR数字滤波器的设计与如何在DSPOP得到实现进行了研究,介绍Matlab中实现FIR滤波器设计的窗函数法。并结合具体的实例,介绍了如何将Matlab设计的滤波器完成到DSP的FIR滤波器的转化。     

A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines     

Low-Area/Power Parallel FIR Digital Filter Implementations

This paper presents a novel approach for implementing area-efficient parallel (block) finite impulse response (FIR) filters that require less hardware than traditional block FIR filter implementations. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. However, a traditional block filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is important to design parallel FIR filter structures that require less area than traditional block FIR filtering structures. In this paper, we propose a method to design parallel FIR filter structures that require a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing technique is introduced and used to reduce the hardware cost of parallel FIR filters. A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantization process, is introduced and used to produce quantized filters with good spectrum characteristics. By using a combination of fast FIR filtering algorithms, a novel coefficient quantization process and area reduction techniques, we show that parallel FIR filters can be implemented with up to a 45% reduction in hardware compared to traditional parallel FIR filters.     

MATLAB-DSP集成环境下的FIR数字滤波器设计

文章介绍了有限冲激响应（FIR）数字滤波器的原理,以及如何根据工程中所给的参数设计所需的FIR数字滤波器。在MATLAB环境下完成FIR数字滤波器的设计与分析,利用CCSIDE完成数字滤波器的实现,通过CCSLink这一高效的工具完成MATLAB与DSP之间的实时数据传送,在不影响DSP运行的情况下完成DSP的开发。利用这一技术可以快速地对DSP进行控制与调试,极大地缩短了DSP的开发周期,提高了DSP的开发效率。     

采用分布式算法的高速FIR滤波器ASIC设计

对DA算法的FIR滤波器和传统乘加结构FIR滤波器的性能进行了比较,介绍了改进DA算法的原理;对分别采用FPGA和芯片实现的DA算法高速FIR滤波器的性能指标进行了比较;介绍了ASIC芯片设计时存储器的可测性设计方法,以及存储器对布局布线策略的影响。最后,给出了版图形式的设计结果及电路验证信号波形。     

基于MATLAB 7.0的FIR滤波器设计及实现

用窗函数设计法设计FIR滤波器,采用MATLAB7.0具体实现.通过对带通FIR滤波器的具体研究,确立了MATLAB设计FIR滤波器的设计流程,为进一步在定点DSP硬件上的实现奠定基础.此外本文还对在DSP上实现的一些关键问题作了简介.     

一种FIR滤波器的FPGA实现

数字滤波是语音与图像处理和模式识别等应用中的一种基本的数字信号处理部件。文中提出了一种采用FPGA器件并利用窗函数实现线性FIR数字滤波器的方案,使用Xilinx公司的XCS10FPGS器件设计了一个8阶8位FIR滤波器,阶数和位数以及滤波器特性均可方便地更改。     

基于SRFFT算法的FIR数字滤波器设计及ADSP21160实现

基于分裂基FFT(SRFFT)算法设计FIR数字滤波器，首先将输入信号经A／D转换成数字序列，运用重叠相加法将数字序列分段成固定长度的数据组，然后采用SRFFT算法对固定长度的数据组将时域的卷积运算转换为频域的复乘运算，再利用分裂基IFFlT(SRIFFT)转换回时域，从而达到滤波的效果。基于SRFFT算法的FIR数字滤波器较其他FFT算法大量减少了复乘加运算量，提高了滤波效率。本文设计的滤波器是一个长度为400～500阶的可变FIR数字滤波器，输入信号为采样速率10MHz的复数据，根据系统处理要求，采用2片高速浮点芯片ADSP21160构成多处理器并行系统来实现高速FIR数字滤波器的设计。     

基于TMS320VC5509DSP的FIR数字滤波器的实现

FIR数字滤波器广泛应用于实时数字信号处理领域.本文介绍了FIR数字滤波器的结构、特点及设计方法,并采用窗函数法设汁了FIR滤波器.利用TMS320VC5509 DSP芯片强大的数字信号处理功能实现了该滤波器.实验表明,此数字滤波器工作稳定,能够满足实时的滤波处理功能.     

可编程FIR滤波器的FPGA实现

介绍了FIR滤波器的基本的线性相位结构及FIR滤波器的抽头系数SD算法编码。给定滤波器的数字指标,用MATLB设计抽头系数,最后用Verilog HDL语言实现了一个16阶的FIR低通滤波器并在QuartusⅡ上仿真,并对仿真结果与理论值进行比较,波形仿真结果和理论值相吻和,最后将编程数据文件下载到FPGA芯片上。对于不同性能的FIR滤波器,抽头系数是变化的,因此只要对本设计的抽头系数重新在线配置,就可以实现不同的FIR滤波器。     

基于DSP的FIR数字滤波器的设计与实现

FIR数字滤波器广泛地应用于数字信号处理领域,本文对FIR滤波器的工件原理和设计方法进行了简单的介绍。文中采用窗函数法设计FIR数字滤波器,给出了TMS320VC5402的编程语句及其仿真波形。