A sub-1-V 15-ppm/°C CMOS bandgap voltage reference withoutrequiring low threshold voltage device

A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V_thn ≈ |V_thp| ≈ 0.9 V at 0°C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 μA. A temperature coefficient of 15 ppm/°C from 0°C to 100°C is recorded after trimming. The active area of the circuit is about 0.24 mm²     

Internal voltage generator for low voltage, quarter-micrometerflash memories

A fabricated bandgap generator using 0.25-μm Flash memory process generated a stable reference voltage under 4 V, boosted from an external power supply of 2.5 V. The generated voltage was 1.297±0.025 V at a power supply of 4 V±10%; the temperature dependence was +0.7 mV/°C. The characteristics of a triple-well bipolar transistor for the Flash memory process are sufficient for a reference voltage generator; f_T is 230 MHz, and H_FE is 70. Dynamic operation reduced the average current consumption from 306 to 8.6 μA. Fabricated voltage-doubler circuits generated a voltage 1.8 times larger than that from conventional charge-pump circuits     

A tunable CMOS-DRAM voltage limiter with stabilized feedbackamplifier

The authors present two developments for a CMOS-DRAM voltage limiter: a precise internal-voltage generator, and a stabilized driver composed of a feedback amplifier with compensation. The voltage limiter's features include generating a PMOS-V_T difference, being capable of voltage tuning with fuse trimming, and compensation in the driver circuit through zero insertion. It provides a voltage impervious to supply-voltage and substrate-voltage boundings, temperature variation, and process fluctuation, while ensuring the feedback-loop stability with a phase margin of 55° for a time-dependent load of DRAM circuit. The proposed circuits are experimentally evaluated through their implementation in a 16-Mb CMOS DRAM. A temperature dependency of 1.4 mV/°C and a voltage deviation within ±10% for process fluctuation are achieved. The voltage is stabilized within ±3% for V_CC bounce and ±10% for memory operation     

Trimming process and temperature variation in second-order bandgap voltage reference circuits

This paper presents the design and experimental performance of a second-order bandgap voltage reference integrated circuit (IC). Experimentally observed nominal reference voltage at room temperature is 1.150 V with best temperature performance of 3 mV variation over −40 to 120 °C. A 5-bit resistor trimming is used to compensate the variation of reference voltage due to layout mismatch and process variation. A trimming methodology is described in this paper to optimize both the temperature performance and reduce the variation of the room temperature voltage over different samples. Even with best temperature performance trim-code, the absolute variation in reference voltage over 20 samples is 85 mV which is trimmed to ±11 mV (1.3%) using the proposed trimming methodology. The second-order bandgap circuit is designed in a 0.5 μm BiCMOS process with less than 50 μA current consumption.     

A curvature-corrected low-voltage bandgap reference

A curvature-corrected bandgap reference that can function at supply voltages as low as 1 V, at a supply current of only 100 μA, is presented. After trimming, this bandgap reference has a temperature coefficient (TC) of ±4 p.p.m./°C. The reference voltage is about 200 mV and it can easily be adjusted to higher values. The temperature range of this circuit is from 0 to 125°C. This bandgap reference is realized using a standard bipolar process with base-diffused resistors     

A CMOS pulse-width modulator/pulse-amplitude modulator forfour-quadrant analog multipliers

A CMOS pulse-width modulator/pulse-amplitude modulator (PWM/PAM) has been designed using the Tomota-Sugiyama-Yamaguchi principle. The PWM/PAM has been used to build a four-quadrant analog multiplier (4-QAM) with a DC transfer function that depends only on resistor matching and on the value of a reference voltage. The PWM/PAM circuit was fabricated in a 3-μm CMOS process; measurements show a small total error (maximum 2% of full scale) without trimming, a high temperature stability (±6 ppm/°C), and a low supply voltage sensitivity (±25 ppm/%). The total harmonic distortion of the PWM is less than 0.05% (measured for a clock frequency of 200 kHz). Analytic design equations include a DC error model, a stability criterion, and the relation between the maximum bandwidth and the clock frequency     

具有负反馈的分段曲率校正CMOS带隙基准源

提出了一种新型带有负反馈的分段曲率校正带隙电压基准源,该基准源的主要特色是利用温度相关的电阻比技术获得一个分段曲率校正电流,校正了一阶带隙基准源的非线性温度特性.该分段线性电流产生电路还形成了一个负反馈,以改善带隙基准源的电源抑制和线性调整率.测试结果表明:在2.6V电源电压下,该基准源在没有采用校正的条件下,在-50～125℃温度范围内实现了最大21.2ppm/℃温度系数,电源抑制比为-60dB.在2.6～5.6V电源电压下的线性调整率为0.8mV/V.采用中芯国际(SMIC)0.35μm5Vn阱数字CMOS工艺成功实现,有效芯片面积0.04mm2,其总功耗为0.18mW.该基准源应用于3,5V兼容的光纤接收跨阻放大器.     

一种新型CMOS电流模带隙基准源的设计

设计了一种新型电流模带隙基准源电路和一个3bit的微调电路。该带隙基准源可以输出可调的基准电压和基准电流,避免了在应用中使用运算放大器进行基准电压放大和利用外接高精度电阻产生基准电流的缺点,同时该结构克服了传统电流模带隙基准源的系统失调、输出电压的下限限制以及电源抑制比低等问题。该带隙基准源采用0.5μm CMOS混合信号工艺进行实现,有效面积450μm×480μm;测试结果表明在3 V电源电压下消耗1.5mW功耗,电源抑制比在1 kHz下为72dB,当温度从-40～85°C变化时,基准电压的有效温度系数为30×10-6V/°C。该带隙基准电路成功应用在一款高速高分辨率模数转换器电路中。     

A switched-current, switched-capacitor temperature sensor in0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT δV_BE signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25° from -55°C to 125°C with an error of less than 1°. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 μA. The supply voltage is 2.7-5.5 V     

CMOS magnetic-field sensor system

A magnetic-field sensor system integrated in CMOS technology with additional processing steps necessary for sensor fabrication is presented. The system contains a magnetoresistive permalloy microbridge acting as a sensor, temperature compensation circuitry, programmable readout electronics, reference voltage bias, and clock generation. It features maximum magnetic flux sensitivity of 70 mV/μT (corresponds to the magnetic-field sensitivity of 88.2 mV/(A/m) at μ_r=1) and its temperature gain is below 260 ppm/°C in the range between -50°C and +100°C     

A BiCMOS speech circuit with only two external components

A telephone chip that performs all the basic functions of a speech circuit using only two external components is reported. Precision filtering based on switched-capacitor (SC) techniques is used to implement on-chip impedance termination, hybrid with sidetone cancellation, and DC characteristics starting from a single 1% external resistor. A new low-drop on-chip voltage supply generator derived from the line using an external storage capacitor is also realized. Better than 33-dB impedance matching and more than 30-dB sidetone cancellation is achieved without any external trimming. The TX linearity is better than 50 dB up to 4.4 V_p-p on the line. The chip has an active area of approximately 2.6 mm² and draws 1.5 mA of quiescent current     

High-temperature storage and thermal cycling studies of thick filmand wirewound resistors

The operating ambient temperature for underhood automotive and aerospace applications is increasing. This work was undertaken to evaluate the suitability of thick film and wirewound resistors for distributed aircraft control systems in a 200°C-225°C operating environment. High temperature stability testing of power wirewound and thick film resistors is reported. Dale power wirewound 1 Ω, 100 Ω, and 10 kΩ resistors with power ratings of 5 W and 25 W were tested. The TCR of the 100 Ω, and 10 kΩ resistors was very small, however, the 1 Ω resistor varied by 5% over the temperature range from 25°C to 300°C. Stability with long term storage (10000 h) at 300°C was measured for the wirewound resistors unpowered and powered at 20% of rated power. With the exception of the 10 kΩ/25W resistor, the change in resistance was less than 4%. Wirewound resistors were also thermal cycled 1000 times over a temperature range from -55°C to 225°C with only one failure due to a broken internal connection. Three 900 Series thick film resistor pastes from Heraeus-Cermalloy were studied: 100 Ω/sq., 1 kΩ/sq., 10 kΩ/sq. The temperature coefficient of resistance (TCR) was measured from 27°C to 500°C in 50°C increments. The change in resistance was <±6% up to 300°C. A 2 × 2 matrix of variables was included in the 300°C storage test: untrimmed resistors, resistors trimmed up 50% in value, unpowered, and powered at 1/8 W. Palladium/Silver was the initial termination choice for these 300°C studies, but silver migration under electrical bias lead to electrical shorts between conductor traces on the substrates with powered resistors. Gold terminated thick film resistors were used for powered storage testing at 300°C. The change in resistance after 10000 h at 300°C was < 3% for all test combinations     

700-V asymmetrical 4H-SiC gate turn-off thyristors (GTO's)

Silicon Carbide (4H-SiC), asymmetrical gate turn-off thyristors (GTO's) were fabricated and tested with respect to forward voltage drop (V_F), forward blocking voltage, and turn-off characteristics. Devices were tested from room temperature to 350°C in the dc mode. Forward blocking voltages ranged from 600-800 V at room temperature for the devices tested. V_F of a typical device at 350°C was 4.8 V at a current density of 500 A/cm². Turn-off time was less than 1 μs. Although no beveling or advanced edge termination techniques were used, the blocking voltage represented approximately 50% of the theoretical value when tested in an air ambient. Also, four GTO cells were connected in parallel to demonstrate 600-V, 1.4 A (800 A/cm ²) performance     

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

A Temperature Compensated Exponential Function Generator

An exponential function generator using the relation between emitter-base voltage and collector current of a silicon transistor is described briefly. The inherent temperature dependence is greatly reduced by using an emitter coupled pair of transistors and one temperature dependent resistor. The exponential range covers about 9 decades of current at 60 /spl deg/ C.     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

A precise on-chip voltage generator for a gigascale DRAM with anegative word-line scheme

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-μm process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V_BB bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's     

A 4-Mb pseudo SRAM operating at 2.6±1 V with 3-μA dataretention current

A 4-Mb pseudo static RAM (PSRAM) suitable for universal battery usage is described. The wide voltage range, 2.6±1 V, is set to target the power supply voltage of the PSRAM considering various voltage levels and charging-discharging characteristics of batteries. A double-to-single automatically switchable booster is developed to provide the wide voltage range operation. To reduce the power dissipation of data retention for battery usage a low-power back-bias generator with a new substrate-level sensor and a temperature-dependent self-refresh timer with a unique internal refresh control scheme are demonstrated. A PSRAM operation ranging from 1 V to more than 5 V was obtained and a 3-μA data retention current was realized at room temperature in contrast with 7 μA at 70°C and V_cc of 2.6 V. This PSRAM allows a 20-Mbyte RAM disk to retain data for two months with a single lithium battery     

A CMOS bandgap reference for differential signal processing

A switched-capacitor fully differential bandgap reference that uses a standard double-poly CMOS process is presented. It generates a differential reference voltage of 6.2 V with a standard deviation of about 24 mV and a typical temperature stability of 15.2 p.p.m./°C over an extended temperature range from -40 to +85°C. These performance results are obtained without using any trimming in mass production. The bandgap reference only occupies 730 mil² and dissipates 4.8 mW at±5-V power supplies. A measured power supply rejection of about 90 dB until 500 kHz is the best ever reported at high frequency     

一种基于BCD工艺的宽压-宽温电流基准电路

设计了一种基于BCD工艺的宽压-宽温电流基准电路.利用片上多晶硅电阻的温度系数受工艺影响较小的特点,选定其为基准电流定义单元.分析片上电阻温度特性,并设计与其温度系数相等的参考电压,加载到电阻上,从而实现了温度系数很低的基准电流.分析了高温下三极管寄生元件漏电现象,通过添加补偿管,提高了基准电流在高温下的稳定性.电流基...