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An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead. 相似文献
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This paper presents a partial scan methodology suited for (pipelined) data paths described at the Register-Transfer level. The method is based on feedback elimination by making existing registers scannable or by adding extra transparent scan registers An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. This approach can deal with complex realistic data paths requiring orders of magnitude lower CPU times than gate devel techniques. Furthermore, our symbolic test pattern generation technique can very effectively deal with the delay in the remaining acyclic sequential circuit parts. This symbolic test method makes various scan schemes possible which ensure a correct assembly and application of the test vectors. They are discussed and compared in terms of hardware requirements, test application times and test accuracy. 相似文献
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介绍了几种主要的VLSI可测性设计技术,如内部扫描法、内建自测试法和边界扫描法等,论述如何综合利用这些方法解决SOC内数字逻辑模块、微处理器、存储器、模拟模块、第三方IP核等的测试问题,并对SOC的可测性设计策略进行了探讨. 相似文献
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A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing 总被引:1,自引:0,他引:1
This paper introduces a new multi-mode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Concurrent with normal operation, the design can accumulate a signature of the state variables in the scan-register configured as a multiple input signature analyzer (MISA). Thus virtually complete state observability is achieved without the need of scanning-out the state for each test-input. The pseudorandom states of the MISA can also be utilized as state inputs in pseudorandom testing. In this way, most faults are covered in a pseudorandom, test per clock mode. Only a few random pattern resistant faults require scan, greatly reducing test application time. Pseudorandom delay testing of the true normally active circuit paths is also possible. Two-pattern tests are supported. Finally, we show that the new memory element can also be used for fault-tolerant design. 相似文献
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Register-transfer level designs that are derived from high-level synthesis systems generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximize resource sharing These multiplexer and bus structures have the unique ability to behave asswitches, i.e., to logically partition the circuit when their control inputs are manipulated in different ways. The presence of switches, the selection of scan registers can be influenced. This leads to an efficient partial scan methodology presented in this paper. Second, switches help set up data transfer paths calledI-paths. By employingI-paths to transport test data, the functional logic in the circuit can be separated from the switching logic for the purpose of test generation. This can lead to a reduction in test generation costs for a partial scan design. Thus the techniques presented in this paper help to minimize both testability overhead and test generation cost in bus-based circuits. This methodology is implemented in the SIESTA system for serial scan design. 相似文献
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This paper deals with a design methodology and associated architecture to support the control of on-chip DFT and BIST hardware. The work is general in that it supports numerous test methods, such as partial and full scan, multiple and reconfigurable scan chains, and both test per clock BIST and scan BIST. The results presented here are compatible with the IEEE 1149.1 boundary scan architecture. The work is based on a hierarchical control methodology that includes systems, PCBs and MCMs. Various options for assigning control functions to be on-chip or off-chip are described. A new, partially distributed test control architecture is introduced that includes an internal test bus and distributed local controllers. There are three main modes of control of test resources, namely local static control, dynamic control and global static control. We show how the control mechanism can be implemented together with the IEEE 1149.1 test protocol. The synthesis of the on-chip test control hardware has been automated in a system called CONSYST. 相似文献
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扫描链测试,作为一种简单、高效的可测性设计方法,已经广泛应用于集成电路设计中。该方法可以有效地检测出电路制造过程中的缺陷和故障,从而降低芯片的测试成本。但是随着扫描链的插入,芯片物理设计中的时序收敛变得更加复杂,尤其是在扫描链测试的移位模式下,由于时钟偏移的存在,保持时间可能存在大量的时序违例。针对这种情况,本文首先介绍了扫描链测试的基本原理,分析了插入扫描链之后出现保持时间违例的原因,提出了一种基于锁存器的修复时序违例的方法,并详细阐述了对于不同边沿触发的触发器组如何选择相应的锁存器实现时序收敛。最后,将该方法应用于一款电力通信芯片的物理设计,快速、高效地实现了时序的收敛。 相似文献
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Yu Huang Chien-Chung Tsai Nilanjan Mukherjee Omer Samman Wu-Tung Cheng Sudhakar M. Reddy 《Journal of Electronic Testing》2002,18(2):189-201
This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered. 相似文献
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This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead. 相似文献
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提出了扫描法可测性设计中扫描触发器的最优实现方法,采用该方法每个触发器仅需增加2个MOS管即可构成扫描触发器,比用传统方法减少12个MOS管,而增加的额外管脚数与传统方法一样。这样,即使采用全扫描设计,也仅需较小的芯片面积。 相似文献
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Nagle H.T. Roy S.C. Hawkins C.F. McNamer M.G. Fritzemeier R.R. 《Industrial Electronics, IEEE Transactions on》1989,36(2):129-140
A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered 相似文献
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介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求. 相似文献
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高频锁相环的可测性设计 总被引:1,自引:1,他引:0
文章针对一款应用于大规模数字集成电路的CMOS高频锁相环进行了可测性设计,详细讨论了最高输出频率、输出频率范围和锁定时间等参数的测试.分别给出了边界扫描测试和分频器测试两种测试方案,并对两种方案进行了比较,指出了各自的适用范围.对于选用的边界扫描方法,给出了详尽的测试电路图,并进行了电路仿真,仿真结果表明该方法有效可行. 相似文献
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DFT技术已经成为集成电路设计的一个重要组成部分.详细介绍了基于扫描测试的DFT原理和实现步骤,并对一个32位FIFO存储器电路实例进行扫描设计.根据扫描链的特点和电路多时钟域问题,采用了三种设计方案,整个流程包括了行为级Verilog代码的修改、扫描设计综合以及自动测试模板产生(ATPG).对不同的设计方案给出了相应的故障覆盖率,并对生成的模板进行压缩优化,减少了测试仿真时间.最后分析了导致故障覆盖率不同的一些因素和设计中的综合考虑. 相似文献
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This paper presents an efficient estimation method for incremental testability analysis, which is based partially on explicit testability re-calculation and partially on gradient techniques. The analysis results have been used successfully to guide design transformations and partial scan selection. Experimental results on a variety of benchmarks show that the quality of our incremental testability analysis is similar to those of the conventional explicit testability re-calculation methods and the technique can be used efficiently for improving the testability of a design during the high-level test synthesis and partial scan selection processes. 相似文献