一种基于存储器故障原语的March测试算法研究

研究高效率的系统故障测试算法,建立有效的嵌入式存储器测试方法,对提高芯片良品率、降低芯片生产成本,具有十分重要的意义.从存储器基本故障原语测试出发,在研究MarchLR算法的基础上,提出March LSC新算法.该算法可测试现实的连接性故障,对目前存储器的单一单元故障及耦合故障覆盖率提升到100%.采用March LSC算法,实现了内建自测试电路(MBIST).仿真实验表明,March LSC算法能很好地测试出嵌入式存储器故障,满足技术要求.研究结果具有重要的应用参考价值.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Test generation and scheduling for layout-based detection of bridgefaults in interconnects

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors     

一种Mbist新型算法March 3CL的设计

制造工艺的不断进步,嵌入式存储器在片上系统芯片中的集成度越来越大,同时存储器本身也变得愈加复杂,使得存储器出现了一系列新的故障类型,比如三单元耦合故障.存储器內建自测试技术是当今存储器测试的主流方法,研究高效率的Mbist算法,是提高芯片成品率的必要前提.以SRAM的7种三单元耦合故障为研究对象,通过分析故障行为得到三单元耦合的72种故障原语,并且分析了地址字内耦合故障的行为,进而提出新的测试算法March 3CL.以2048X32的SRAM为待测存储器,利用EDA工具进行了算法的仿真,仿真结果表明,该算法具有故障覆盖率高、时间复杂度低等优点.     

New March Tests for Multiport RAM Devices

This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2ⁿ-bit decoder (with column multiplexers for the column addresses) and drivers, and a K-bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST implementation with a modest area overhead that tests these faults and achieves low test application time.     

Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.     

Testing of three-stage switching networks for coupling faults

A coupling fault diagnosis procedure is proposed for digital switching networks constructed of uniform time-division switches. The procedure is executed in two phases. Each phase consists of eight test steps; the number of tests for detecting the most likely coupling faults inside a single switch is independent of the network size. The concept of primitive and convolutional test vectors is introduced in order to analyze test stimuli applied to successive switches during the test. The approach can be easily adapted for use in many modern digital exchanges     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

Diagnostic Test Set Minimization and Full-Response Fault Dictionary

We minimize a given test set without loss of diagnostic resolution in full-response fault dictionary. An integer linear program (ILP), formulated from fault simulation data, provides ultimate reduction of test vectors while preserving fault coverage and pair-wise distinguishability of faults. The complexity of the ILP is made manageable by two innovations. First, we define a generalized independence relation between pairs of faults to reduce the number of fault pairs that need to be distinguished. This significantly reduces the number of ILP constraints. Second, we propose a two-phase ILP approach. In the first phase, using an existing procedure, we select a minimal detection test set. In the second phase, additional tests are selected for the undiagnosed faults using a newly formulated diagnostic ILP. The overall minimized test set may be only slightly longer than a one-step ILP optimization, but has advantages of reducing the minimization problem complexity and the test time required by the minimized tests. Benchmark results show potential for significantly smaller diagnostic test sets.     

Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.     

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log₂ n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.Supported by C&C Research Laboratories, NEC USA, during summer 1991.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Failure Analysis of Memory Organization for Utilization in a Self-Repair Memory System

Traditional approaches to memory reliability have been limited to complete redundancy or coding techniques. Redundancy frequently proves too expensive (introducing additional systems faults) and the traditional memory coding techniques have been limited to those areas of memory where a single fault results in a single failure (e.g., a broken core in a magnetic memory) as distinguished from an address decoder fault. To take an integrated approach to this problem, using a variety of coding and modularization techniques on each of the memory subsystems, it is necessary to determine the types of faults and failures caused by these faults that could occur in the system. This paper presents the results of a failure analysis study of typical 2D, 2?D, and 3D memory organizations. Two-way memories are also considered. This study demonstrates that a 2D memory, utilizing a switching array for memory access, is less susceptible to eatastrophic failures than other organizations considered. A memory organization capable of distributing the failures, in a manner permitting correction by linear codes, was adopted. Other techniques for automatic replacement of fault units are also considered.     

Techniques for Disturb Fault Collapsing

Disturb faults are considered one the most important failure modes in non volatile memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization. In this paper, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs and to create a reduced fault list. To demonstrates its effectiveness, the method was used to create minimized fault lists for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms. This work was supported by Kuwait University Research Grant Number EO 01/04.     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.     

Test Challenges in Nanometer Technologies

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.     

Analysis of Resistive Open Defects in Drowsy SRAM Cells

New fault behaviors can emerge with the introduction of a drowsy mode to SRAMs. In this work, we show that, in addition to the data-retention faults that can occur during the drowsy mode, open defects in SRAM cells can also result in new fault behaviors when a memory is accessed immediately after wake-up. We first describe these new read-after-drowsy (RAD) fault behaviors and derive their corresponding fault primitives (FPs). Then, we propose a new March test, called March RAD, by inserting drowsy operations to a traditional test algorithm. Finally, the impact of the standby supply voltage on triggering the drowsy faults in SRAM cells is investigated. It is shown that, as the supply voltage is reduced in the drowsy mode to further cut down leakage, open defects with a parasitic resistance as small as 100 K Ω begin to cause faults.     

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.     

A transparent online memory test for simultaneous detection of functional faults and soft errors in memories

The Transparent Online Memory Test (TOMT) introduced here has been specifically developed for online testing of word-oriented memories with parity or Hamming protection. Careful interleaving of a word-oriented and a bit-oriented test facilitates a fault coverage and a test duration comparable to the widely used March C- algorithm. Unlike similar methods TOMT actively exercises all bit cells in memory within one test period. Hence it not only detects soft errors but also functional faults and reliably prevents fault accumulation. Different variants of the basic TOMT algorithm are investigated in terms of fault coverage and test time. A prototype implementation for SRAM is introduced which-integrated into a standard processor/memory interface-autonomously performs the transparent online memory test. The trade-offs in terms of hardware overhead and memory access delay caused by this system integration are explored.     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。