Applications of Algebraic Soft-Decision Decoding of Reed–Solomon Codes

Efficient soft-decision decoding of Reed–Solomon codes is made possible by the Koetter–Vardy (KV) algorithm which consists of a front-end to the interpolation-based Guruswami–Sudan list decoding algorithm. This paper approaches the soft-decision KV algorithm from the point of view of a communications systems designer who wants to know what benefits the algorithm can give, and how the extra complexity introduced by soft decoding can be managed at the systems level. We show how to reduce the computational complexity and memory requirements of the soft-decision front-end. Applications to wireless communications over Rayleigh fading channels and magnetic recording channels are proposed. For a high-rate (RS 9225,239) Reed–Solomon code, 2–3 dB of soft-decision gain is possible over a Rayleigh fading channel using 16-quadrature amplitude modulation. For shorter codes and at lower rates, the gain can be as large as 9 dB. To lower the complexity of decoding on the systems level, the redecoding architecture is explored which uses only the appropriate amount of complexity to decode each packet. An error-detection criterion based on the properties of the KV decoder is proposed for the redecoding architecture. Queuing analysis verifies the practicality of the redecoding architecture by showing that only a modestly sized RAM buffer is required.     

Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are one of the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to hard-decision decoding, soft-decision decoding offers considerably higher error-correcting capability. The Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while maintaining a complexity polynomial with respect to the code word length. In the KV algorithm, the interpolation step dominates the decoding complexity. A reduced complexity interpolation architecture is proposed in this paper by eliminating the polynomial updating corresponding to zero discrepancy coefficients in this step. Using this architecture, an area reduction of 27% can be achieved over prior efforts for the interpolation step of a typical (255, 239) RS code, while the interpolation latency remains the same     

Fast factorization architecture in soft-decision Reed-Solomon decoding

Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koetter-Vardy (KV) algorithm can achieve substantial coding gain for high-rate RS codes, while maintaining a polynomial complexity with respect to the code length. In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed in this paper to speed up the factorization step. As a result, the time-consuming exhaustive-search-based root computation in each iteration level, except the first one, of the factorization step is circumvented with more than 99% probability. Using the proposed architecture, a speedup of 141% can be achieved over prior efforts for a (255, 239) RS code, while the area consumption is reduced to 31.4%.     

Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in digital communication and storage systems. Among the decoding algorithms of RS codes, the recently developed Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while has a polynomial complexity. One of the major steps of the KV algorithm is the factorization. Each iteration of the factorization mainly consists of root computations over finite fields and polynomial updating. To speed up the factorization step, a fast factorization architecture has been proposed to circumvent the exhaustive-search-based root computation from the second iteration level by using a root-order prediction scheme. Based on this scheme, a partial parallel factorization architecture was proposed to combine the polynomial updating in adjacent iteration levels. However, in both of these architectures, the root computation in the first iteration level is still carried out by exhaustive search, which accounts for a significant part of the overall factorization latency. In this paper, a novel iterative prediction scheme is proposed for the root computation in the first iteration level. The proposed scheme can substantially reduce the latency of the factorization, while only incurs negligible area overhead. Applying this scheme to a (255, 239) RS code, speedups of 36% and 46% can be achieved over the fast factorization and partial parallel factorization architectures, respectively.     

RS码译码算法对比研究

RS码所具有的高效译码性能使其被广泛应用于数据通信和存储系统的差错控制中。本文主要对目前常用的RS码的硬判决译码算法和K—V代数软判决译码算法进行对比研究。通过对两种算法原理的理论分析,给出了RS码在硬判决与软判决的算法下的计算机仿真。结果表明两种算法均能得到良好的译码效果,而软判决译码算法较硬判决方式能更有效地带来系统增益。而软判决译码算法可以通过适当提高复杂度来改善系统的性能。     

Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed–Solomon Decoding

Reed-Solomon codes are powerful error-correcting codes that can be found in many digital communications standards. Recently, there has been an interest in soft-decision decoding of Reed-Solomon codes, incorporating reliability information from the channel into the decoding process. The Koetter-Vardy algorithm is a soft-decision decoding algorithm for Reed-Solomon codes which can provide several dB of gain over traditional hard-decision decoders. The algorithm consists of a soft-decision front end to the interpolation-based Guruswami-Sudan list decoder. The main computational task in the algorithm is a weighted interpolation of a bivariate polynomial. We propose a parallel architecture for the hardware implementation of bivariate interpolation for soft-decision decoding. The key feature is the embedding of both a binary tree and a linear array into a 2-D array processor, enabling fast polynomial evaluation operations. An field-programmable gate array interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mb/s     

Bandwidth efficient communication via a Rayleigh fading channelusing RS coded multiphase signaling

The idea of combining RS (Reed-Solomon) codes with multiphase signaling schemes on fading channels is introduced. The performance of these schemes over a Rayleigh fading channel is evaluated for different decoding strategies, i.e., errors-only, errors-and-erasures, and soft-decision decoding techniques. Both analytical and simulation results show that substantial coding gains are obtained compared to the uncoded reference system     

Iterative algebraic soft-decision list decoding of Reed-Solomon codes

In this paper, we present an iterative soft-decision decoding algorithm for Reed-Solomon (RS) codes offering both complexity and performance advantages over previously known decoding algorithms. Our algorithm is a list decoding algorithm which combines two powerful soft-decision decoding techniques which were previously regarded in the literature as competitive, namely, the Koetter-Vardy algebraic soft-decision decoding algorithm and belief-propagation based on adaptive parity-check matrices, recently proposed by Jiang and Narayanan. Building on the Jiang-Narayanan algorithm, we present a belief-propagation-based algorithm with a significant reduction in computational complexity. We introduce the concept of using a belief-propagation-based decoder to enhance the soft-input information prior to decoding with an algebraic soft-decision decoder. Our algorithm can also be viewed as an interpolation multiplicity assignment scheme for algebraic soft-decision decoding of RS codes.     

Forward Error Correction Coding for Fading Compensation in Mobile Satellite Channels

Fading in mobile satellite communications severely degrades the performance of data transmission. The channel is modeled with nonfrequency selective Rice and Rayleigh fading. Also, stored channel simulation is used for hardware data transmission. FEC coding with Viterbi decoding of convolutional codes, and Berlekamp-Massey decoding of Reed-Solomon codes, are used to compensate for the fading. In addition to interleaving, channel state and erasure information improve the performance of the decoder. The BER after decoding is calculated for specific codes on several channels and for different transmission schemes. Using very simple channel state and erasure information gives 2-7 dB additional coding gain. These gains have been verified by hardware data transmission on synthetic fading channels and stored mobile satellite channels.     

Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes

Reed–Solomon (RS) codes have very broad applications in digital communication and storage systems. The recently developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. ASD algorithms consist of two major steps: the interpolation and the factorization. In this paper, novel architectures for both steps are proposed for the BGMD decoder. The interpolation architecture is based on the newly proposed Lee-O'Sullivan (LO) algorithm. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 25% higher efficiency in terms of speed/area ratio than prior efforts. Root computation over finite fields and polynomial updating are the two main steps of the factorization. A low-latency and prediction-free scheme is introduced in this paper for the root computation in the BGMD decoder. In addition, novel coefficient storage schemes and parallel processing architectures are developed to reduce the latency of the polynomial updating. The proposed factorization architecture is 126% more efficient than the previous direct root computation factorization architecture.      

High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes

Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. In this paper, we present a hybrid data format-based interpolation architecture that is well suited for high-speed implementation of the soft-decision decoders. It will be shown that this architecture is highly scalable and can be extensively pipelined. It also enables maximum overlap in time for computations at adjacent iterations. It is estimated that the proposed architecture can achieve significantly higher throughput than conventional designs with equivalent or lower hardware complexity     

A Reed-Solomon coded DS-CDMA system using noncoherent M-aryorthogonal modulation over multipath fading channels

The performance of Reed-Solomon (RS) coded direct-sequence code division multiple-access (DS-CDMA) systems using noncoherent M-ary orthogonal modulation is investigated over multipath Rayleigh fading channels. Diversity reception techniques with equal gain combining (EGC) or selection combining (SC) are invoked and the related performance is evaluated for both uncoded and coded DS-CDMA systems. “Errors-and-erasures” decoding is considered, where the erasures are based on Viterbi's (1982) so-called ratio threshold test (RTT). The probability density functions (PDF) of the ratio associated with the RTT conditioned on both the correct detection and erroneous detection of the M-ary signals are derived. These PDFs are then used for computing the codeword decoding error probability of the RS coded DS-CDMA system using “errors-and-erasures” decoding. Furthermore, the performance of the “errors-and-erasures” decoding technique employing the RTT is compared to that of “error-correction-only” decoding refraining from using side-information over multipath Rayleigh fading channels. As expected, the numerical results show that when using “errors-and-erasures” decoding, RS codes of a given code rate can achieve a higher coding gain than without erasure information     

Reliability-Based Forward Recursive Algorithms for Algebraic Soft-Decision Decoding of Reed--Solomon Codes

We propose efficient forward recursive algorithms for algebraic soft-decision list decoding of Reed-Solomon codes, which utilize channel reliability information, and outperform the Koetter-Vardy (KV) algorithm with lower decoding latency. We evaluate the performance of the proposed decoding algorithms on additive white Gaussian noise and partial response channels. Simulation results show that we can achieve better performance on a modified extended-extended partial response class 4 channel than on the best possible performance of the KV algorithm, as given by the asymptotic bound for high-rate codes.     

Trellis decoding of combined diversity-coding scheme (MLSD) forfading channels

The performance of a receiver using a combination of soft-decision decoding and diversity reception is investigated for nonselective multipath Rayleigh fading channels. A new scheme for soft-diversity, soft-decision detection, maximum likelihood selection and decoding (MLSD), is introduced, in which decisions on the diversity channels and decoding are carried out simultaneously by using a trellis and the Viterbi algorithm     

On the performance and complexity of A generalized minimum distance reed–solomon decoding algorithm

The article reports on the characteristics of an algorithm that implements generalized minimum distance (GMD) decoding of Reed-Solomon codes. The algorithm uses the novel Welch-Berlekamp (WB) algorithm, as modified by Tze-Hua, in order to minimize the complexity of the decoder. Both the WB algorithm and the GMD extension of the WB algorithm are described in outline. The performance of the GMD algorithm was simulated on AWGN channels and fading channels. Results are presented both for RS and concatenated RS codes. The gains over conventional decoding are larger for fading channels than for AWGN conditions but seem useful in all cases. The complexities of the GMD algorithm and the WB algorithm are analysed and compared to that of conventional RS decoding algorithms.     

基于低密度校验码的OFDM编码调制译码算法

低密度校验码(LDPC)具有编码增益高、译码速度快、性能接近Shannon限的优点。LDPC码应用于OFDM，能有效地提高多径环境下OFDM的BER性能。本文首先简单介绍LDPC码及其概率域上的译码算法，在此基础上对译码算法作融合，阐述概率似然比的译码算法。为了把LDPC应用于OFDM系统上，提出了多电平调制下的LDPC译码的算法。仿真结果表明，在AWGN和Rayleigh信道下，此算法正确有效。     

Variable-bit-rate speech transmission using punctured convolutionalcodes

Rate (n-1)/n punctured convolutional codes are very effective in conjunction with embedded differential pulse code modulation (EDPCM) in variable-bit-rate speech transmission. The authors investigate the performance of this variable-bit-rate EDPCM system in terms of probability of bit error and audio signal-to-noise ratio (SNR) versus channel SNR in an additive white Gaussian noise and Rayleigh fading channel using soft-decision decoding for specific sets of code generators of punctured convolutional codes. The results show that different sets of code generators affect the performance in terms of both the probability of bit error and the audio SNR. Improvements were obtained in the cases of Gaussian nonfading and Rayleigh fading channels using soft-decision decoding     

MDPSK-OFDM with highly power-efficient block codes forfrequency-selective fading channels

This paper investigates the performance of M-ary differential phase shift keying orthogonal frequency-division multiplexing (MDPSK-OFDM) systems employing peak power controlling block codes over frequency-selective Rayleigh fading channels. The block codes have a capability of both error correction and reduction of the peak-to-average power ratio (PAPR). To decode the block codes with reasonable complexity, the extended version of the ordered statistic decoding of Fossorier and Lin (see IEEE Trans. Inform. Theory, vol.41, p.1379-96, 1995) is utilized. The bit error rate performance of the block codes is evaluated over typical indoor radio channels by computer simulation and compared with that of the equivalent frequency diversity of the repetition codes. The significant coding gain and improvement of the irreducible error floor are observed under the constraint of the PAPR from 3 to 6 dB     

Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed–Solomon Codes

Bivariate polynomial factorization is an important stage of algebraic soft-decision decoding of Reed-Solomon (RS) codes and contributes to a significant portion of the overall decoding latency. With the exhaustive search-based root computation method, factorization latency is dominated by the root computation step, especially for RS codes defined over very large finite fields. The root-order prediction method proposed by Zhang and Parhi only improves average latency, but does not have any effect on the worst-case latency of the factorization procedure. Thus, neither approach is well-suited for delay-sensitive applications. In this paper, a novel architecture based on direct root computation is proposed to greatly reduce the factorization latency. Direct root computation is feasible because in most practical applications of algebraic soft-decision decoding of RS codes, enough decoding gain can be achieved with a relatively low interpolation cost, which results in a bivariate polynomial with low Y-degree. Compared with existing works, not only does the new architecture have a significantly smaller worst-case decoding latency, but it is also more area efficient since the corresponding hardware for routing polynomial coefficients is eliminated.     

迭代硬判决反馈的LDPC级联MDPSK解调译码算法

该文给出了瑞利衰落信道条件下LDPC级联MDPSK的接收机结构,研究了在不考虑信道状态条件下基于硬判决反馈的迭代检测译码算法,该算法相对于传统的差分解调和译码,复杂度几乎没有增加。仿真结果表明,这种方法在迭代4次的情况下,在误比特率为10-4时与传统的解调方法相比,可以提供2.2dB的增益。