Effect of the annealing conditions on the electrical characteristics of p+/n shallow junctions

Shallow p+/n junctions are produced by low-energy (10-keV) boron implantation into amorphous silicon layers formed by a prior implantation of Si+ ions. Junctions about 0.1 µm deep with good electrical characteristics (reverse current density Jr< 10^-7A/cm²at - 1 V) are obtained both by electron-beam annealing (1100°C, 2 s) and conventional furnace annealing (800°C, 30 min). It is shown that, in the case of the furnace treatment, lower annealing temperatures produce very high reverse currents, while excellent electrical characteristics (Jr< 10^-8A/cm²) are achieved at higher annealing temperatures (900°C), the junction extending, however, much deeper into silicon (0.26 µm).     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

High-efficiency ion-implanted silicon solar cells

The development of solar cells with AM1 coversion efficiency of 18 percent is reported. The cells comprise an n⁺-p-p⁺structure fabricated from float zone silicon having resistivity of 0.3 Ω . cm. The n⁺and p⁺regions are formed by low energy ion implantation and thermal annealing. An important feature of cell fabrication is the growth of SiO2passivation for reduction of surface recombination velocity. Details of both cell fabrication and testing are reported.     

Avalanche phenomena in 4H-SiC p-n diodes fabricated by aluminum orboron implantation

Characteristics of p-n junction fabricated by aluminum-ion (Al⁺) or boron-ion (B⁺) implantation and high-dose Al⁺-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4×10¹⁵ cm^-2) Al⁺ implantation at 500°C and subsequent annealing at 1700°C, a minimum sheet resistance of 3.6 kΩ/□ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B ⁺-implanted diodes have shown higher breakdown voltages than Al⁺-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 mΩcm² at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence     

Improving radiation hardness of EEPROM/flash cell by N2Oannealing

The effects of an N₂O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co⁶⁰ irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K. However, by adding an N₂ O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K. N₂O annealing also improves the after-irradiation program and erase efficiencies. The N₂O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Laser Annealed and Thermal Annealed Refractory Ohmic Contacts to GaAs

Ohmic contacts to n-type GaAs have been developed for high-temperature device applications up to 300°C. Refractory metallizations were used with epitaxial Ge layers to form the contacts TiW/Ge/GaAs, Ta/Ge/GaAs, Mo/Ge/GaAs, and Ni/Ge/GaAs. Contacts with high dose Si or Se ion implantation (1012 to 1014/cm2) of the Ge/GaAs interface were also investigated. The purpose of this work was to develop refractory ohmic contacts with low specific-contact resistance (~10-6 ?cm2 on 1 x 1017cm-3GaAs) which are free of imperfections, resulting in a uniform n+ doping layer. The contacts were fabricated on epitaxial GaAs layers (n = 2 x 1016 to 2 x 1017 cm-3) grown on n+ ( 2 x 1018 cm-3) or semi-insulating GaAs (at strates. Ohmic contact was formed by both thermal annealing ( at temperatures up to 700°C) and laser annealing (pulsed Ruby). Examination of the Ge/GaAs interface revealed Ge migration into GaAs to form an n+layer. Under optimum laser anneal conditions, the specific contact resistance was in the range 1-5 x 10-6 ?-cm2 (on 2 x 1017cm-3GaAs). Thermally annealed TiW/Ge had a contact resitivity of 1 x 10-6 ? cm2 on 1 x 1017 cm-3 GaAs under optimum anneal conditions. The contacts also showed improved thermal stability over conventional Ni/AuGe contacts at temperatures above 300°C.     

Electrical properties of Ga-implanted Si p+-n shallowjunctions fabricated by low-temperature rapid thermal annealing

p⁺-n shallow-junction diodes were fabricated using on-axis Ga⁶⁹ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1×10¹⁵/cm ², which is in excess of the dosage (2×10¹⁴/cm²) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600°C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm² and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |I/sub off/| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs.     

Junction depth versus sheet resistivity in BF2+-implanted rapid-thermal-annealed silicon

Conditions to achieve shallow p+-junctions with low sheet resistance by using ion implantation and rapid thermal annealing (RTA), are presented. This work shows that (junction depth) × (sheet resistivity)rho_{s}X_{j}has a smaller value with increasing implant dose and anneal temperature (boron solubility), and decreasing implant energy. However, the value is saturated for higher doses than 10¹⁶Xjcm², where Xjis junction depth in micrometers, and anneal temperature should be lower than 1100°C, because of considerable boron diffusion even in 10-s RTA.rho_{s}X_{j} = 18Ω.µm is achieved by BF2+ implantation with 5 × 10¹⁵-cm^-2dose at 30 keV and 1000°C RTA. The possibility of further improvement inrho_{s}X_{j}value is discussed.     

Low loss channel waveguides fabricated in fused silica by germaniumion implantation

The authors report the first low loss channel waveguides (0.10 0.15 dB/cm) formed in fused silica by the implantation of MeV Ge ions. The loss coefficient α was measured as a function of ion dose (8×10¹³-8×10¹⁶ ion/cm²) and annealing temperature (250 to 600°C) at 1300 nm. The as-implanted waveguides exhibited a minimum value of α=0.9 dB/cm at an intermediate range of dose with a reduction to 0.10-0.15 dB/cm after annealing at 500°C     

High quality interpoly-oxynitride grown by NH3nitridation and N2O RTA treatment

In this letter, a method to grow high quality interpolysilicon-oxynitride (interpoly-oxynitride) film is proposed. Samples, nitridized by NH₃ with additional N₂O annealing and CVD TEOS deposited on poly-oxynitride (poly-I) with RTA N ₂O oxidation, show excellent electrical properties in terms of very high electric breakdown field, low leakage current, high charge to breakdown, and low electron trapping rate. This novel film is a good candidate for an interpoly dielectric of future high density EEPROM and flash memory devices     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

离子注入对ITO薄膜电学特性的影响

对系列In2O3∶Sn (ITO)薄膜样品分别实施了不同剂量的Sn+, Ag+ 和Mo+离子注入并将它们在250 ℃下进行了热处理.利用霍耳测量研究了原始样品及注入和退火前后各样品的电学特性.研究了ITO薄膜的电学参数受离子注入的种类及剂量的影响.实验证明不同种类的离子注入会不同程度地降低ITO的导电性能,但热处理的效应与之相反.3种金属中,Sn+离子对薄膜造成的注入损伤最小,而高价的钼离子可以替换铟离子的位置成为施主,当注入剂量为1×1015 cm-2时,经过Mo+离子注入和后续退火的ITO薄膜,载流子浓度提高了14%.     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

Formation of 0.05-μm p+-n and n+-pjunctions by very low (<500 eV) ion implantation

The current-voltage (I-V) characteristics of ultrashallow p⁺ -n and n⁺-p diodes, obtained using very-low-energy (<500-eV) implantation of B and As, are presented. the p⁺-n junctions were formed by implanting B⁺ ions into n-type Si (100) at 200 eV and at a dose of 6×10¹⁴ cm^-2, and n⁺-p junctions were obtained by implanting As⁺ ions into p-type (100) Si at 500 eV and at a dose 4×10¹² cm^-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I-V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm ²⁸Si isotopic layer grown by a low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p⁺-n and n⁺-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8×10^-12 and 2×10^-11 A for p⁺-n and n⁺-p diodes, respectively, using a junction area of 1.96×10^-3 cm²