A decision-feedback equalizer with pattern-dependent feedback formagnetic recording channels

A new nonlinear equalizer for high-density magnetic recording channels is presented. It has a structure of the decision-feedback equalizer (DFE) with a nonlinear model at the feedback section and a dynamic threshold detector. The feedback nonlinear model is a sequence of look-up tables (LUTs) indexed by time, and each table is addressed by a transition pattern formed by one future and ν past transitions. We call this new nonlinear equalizer the pattern-dependent DFE (PDFE). The feedback nonlinear model cancels the trailing nonlinear intersymbol interference (ISI), and then the data decision is made by considering the precursor nonlinear ISI caused by one future symbol. We propose a tap optimization criterion SNR_d for the PDFE which in effect tries to maximize the output signal to noise ratio, and derive a closed-form solution for the tap values. We compare the detection performance of PDFE with that of the DFE and the RAM-DFE on experimental channels. The RAM-DFE is a DFE with one large LUT at its feedback section. The results show that the PDFE yields a significant performance improvement over the DFE and the RAM-DFE. Also the PDFE derived in this paper achieves a superior performance compared with the PDFE derived by the minimum mean-square-error criterion     

A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFEfor magnetic recording

A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm² in a 1 μm CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm² and dissipates 630 mW     

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm~2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.     

一种用于3.3Gbps低功耗高速互连的连续时间自适应模拟均衡器*

设计了适用于多种高速通信指标(USB2.0, PCI-E,Rapid IO)的CMOS模拟均器。通过合并低频和高频支路以降低两个支路的延迟效应,同时均衡滤波器具有比较大的输入阻抗,这有利于通过级联方式来进一步提高高频增益。本文所实现的电路结构在25dB的PCB线路衰减条件下,能够均衡频率范围从1Gbps到3.3Gbps的信号。偏置电路采用复制电路技术,有利于方便的调整主要工作模块的直流工作点。为了抑制前级输出共模对后级电路的影响,在信号的输入端引入了交流耦合。该芯片在0.18um 1P6M工艺下进行了流片验证,整体芯片面积为0.6 x 0.57 mm². 测试结果显示,该模拟均衡器能够在25dB FR4 PCB信道衰减下,对速率为3.3Gbps的信号实现自适应均衡,整体功耗大约为23.4mw.     

High-frequency CMOS continuous-time filters

Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants. A simple, fully differential integrator, optimized for phase-error cancellation, forms the basic element; a complete filter consists of intercoupled integrators. The center frequency of the filter is locked to an external reference frequency by a phase-locked loop. A prototype sixth-order bandpass filter with a center frequency of 500 kHz dissipates 55 mW and occupies 4 mm/SUP 2/ in a 6-/spl mu/m CMOS technology.     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

基于带间干扰模型的音频图示均衡器的设计

图示均衡器传统上由滤波器组实现。由于滤波器组的带间干扰不可避免,传统算法得到的频响曲线与设计要求通常有所偏差,或者是复杂度太大,不适合实时计算。当相邻频段都需要抬升或衰减时,传统算法得到的频响曲线不平坦,有明显波纹。针对此问题,本文研究了滤波器组带间干扰的数学模型,分析了图示均衡器中钟形滤波器的峰值增益与其阻带频响的关系。最后,本文提出了一种基于带间干扰模型的设计方法,利用数值计算列出了参考值,降低了算法复杂度,获得了较为平坦的频响曲线。     

A CMOS switched-capacitor variable line equalizer

The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.     

Robust high-accuracy high-speed continuous-time CMOS currentcomparator

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns at 50 nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

A simple continuous-time equalizer for use in magnetic storage readchannels

A four-pole continuous-time equalizer has been developed to minimize the error rate in rigid-disk magnetic storage channels employing peak detection at high recording densities. The design process consisted of two parts. A nominal model of the disk drive characteristics in the time and frequency domains was obtained from digitized waveforms at the output of a read-head amplifier in a disk drive system. The relative performance of candidate equalizers was studied by subjecting them to the measured data waveforms and then either estimating or measuring the resulting bit error rate in a simulated peak detector, operating on the equalized waveforms. The equalizer outperforms more complex structures proposed for this task and is well suited for implementation as an analog CMOS active filter with low power dissipation. Its constellation of four poles and a zero appears to be useful for several types of magnetic media     

High-speed CMOS frequency divider

A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power     

Reliable CMOS adaptive equalizer for short-haul optical networks

A new low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications is presented in this paper. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). A new version of the spectrum-balancing technique is used as an adaptive criterion, achieving a simple and reliable equalization. The proposed system was designed in a cost-effective 0.18-μm CMOS process. Post-layout simulations demonstrate a signal bandwidth enhancement from 100 MHz to 1.23 GHz for this optical channel, with a total power consumption of 14.3 mW.     

High-speed CMOS circuit technique

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz     

Automatic generation of CMOS continuous-time elliptic filters

A procedure for the generation of CMOS, continuous-time, high-frequency g/sub m/-C filters with finite transmission zeros is presented. A third-order elliptic filter with 0.5 dB equiripple passband, 15 MHz cutoff frequency and -23 dB attenuation in the stopband is given as an example. The automatic generation method can be generalised to arbitrary high-order prototypes and higher-frequency filters derived from LC ladders.<>     

An adaptive analog continuous-time CMOS biquadratic filter

An adaptive analog continuous-time biquadratic filter is realized in a 2-μm digital CMOS process for operation at 300 kHz. The biquad implements the notch, bandpass and low-pass transfer functions. The only parameter adapted is the resonant frequency of the biquad, which is identical to the notch frequency and the bandpass center frequency. The update method is based on a least-means-square algorithm which adapts the notch frequency to minimize the power at the notch filter output. The actual update is modified to reduce the circuit complexity to one biquad and one correlator. When the filter is tracking a sinusoid, this update generates a ripple-free gradient that decreases tracking error. Applications include phase-frequency detectors, FM demodulators (linear and frequency shift keying), clock extractors, and frequency acquisition aids for phase-locked loops and Costas loops. Measured results from experimental prototypes are presented. Nonidealities of an all-analog implementation are discussed, along with suggestions to improve performance     

A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers infinite input impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.     

High-speed facsimile with electrostatic recording

Herein is reported a newly developed high-speed facsimile receiver for use over a wide-band transmission line of up to 48 kHz. The main feature of this equipment is low cost and high speed obtained by mechanical scanning. Good quality electrostatic recording has been achieved at a speed of up to 4000 line scans per minute. The circle-to-line converting multistylus made by printed circuit technology is used for the recording head. A single torsional spring-type rotating wire brush is driven directly by a high-frequency multipole hysteresis motor; thus good contact and smooth operation are obtained with light pressure at high scanning speed.     

A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.     

A CMOS line equalizer for a digital subscriber loop

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.