基于结模型的极化石英光纤内建电场分析

用多载流子模型分析了D型石英光纤的热极化过程及耗尽层的形成,分析了氢离子注入及钠离子耗尽层的形成.并把正负电荷的交界处类比为pn结,分别计算了所形成的内建电场大小.最终得出极化完成后石英光纤的二阶非线性效应主要由钠离子的耗尽形成,计算出的内建电场大小约为108 V/m,由此算出的二阶非线性系数的数值在0.10～0.60 pm/V,和实验报道数值符合较好.     

利用半导体PN结模型分析石英玻璃的极化过程

利用半导体PN结偏置过程的理论模型,类比分析了玻璃的热及电场极化过程。理论分析表明,在热及电场极化条件下,正、负电极与玻璃分界面处的电场及电荷分布规律与其在反向、正向偏置的2个PN结处非常相似;利用PN结偏置模型,并考虑玻璃极化过程中电子的作用,修正了极化玻璃中电场分布和载流子运动方程及其边界条件,并解释了一些已有实验现象。     

熔融石英的热及电场诱导机理

详细分析了熔融石英样品经热及电场诱导后 ,建立二阶极化率的机理。该机理表明 ,二阶极化率是由样品耗尽区中偶极子的定向和三阶极化率经强静电场作用共同形成的。在一般条件下诱导 ,前者是主要因素 ;在较高电压诱导时 ,后者是主要因素。推导了二阶极化率的表达式 ,并进行了数值计算。数值结果表明 ,在一般情况下 ,χ3 3 ( 2 ) 约 1pm/V ,χ3 3 ( 2 ) ∶χ3 1( 2 ) 约为 3。理论证明提高诱导的外加电压和选用Na和OH杂质浓度较大的石英材料能提高二阶极化率。     

单边突变p~+n结的非耗尽分析

本文对硅单边突变p~+n结的空间电荷区做了非耗尽地分析.在考虑到两种自由载流子同时存在的条件下,分析了该p~+n结在平衡态及正向偏置下(非大注入)的电位、电场分布及其中自由载流子浓度关系.指出,单边突变p~+n结的空间电荷区由三部分组成,即尖峰超强电场及少于强电场区、自由载流子耗尽区和边界区.井同耗尽近似的结果进行了对比.     

GeS2-Ga2S3-CdS硫系玻璃的电致二阶非线性光学效应

采用熔融-急冷法制备了在可见光区有较高透射率的GeS2-Ga2S3-CdS硫系玻璃,通过麦克尔(Maker)条纹法观察电场-温度场极化的片状样品中的二阶非线性光学效应,并讨论了该效应的机理。结果表明,在270℃极化30 min,当极化电压大于2 kV/mm时,观察到明显的二阶非线性光学效应,且二次谐波强度的大小随极化电压的增大而增大。二次谐波效应的产生是玻璃中的偶极子在电场作用下的取向调整,破坏了玻璃的宏观各向同性所致,二次谐波强度出现最大值的入射角与偶极子的取向调整程度有关。     

等效表面电荷对台面半导体器件钝化的影响

进一步研究了半导体斜角造型p-n结的表面空间电荷层模型与表面耗尽区模型.计算了耗尽情况下p-n结的表面空间电荷密度,分析了等效表面电荷密度对正斜角造型p-n结表面耗尽区的影响.利用聚酰亚胺和聚酯改性漆钝化的晶闸管电学特性证实了等效表面电荷密度对台面半导体钝化的影响.同时,通过分别采用聚酰亚胺和掺氧多晶硅钝化的高压整流管研究表明,基于掺氧多晶硅的钝化结构具有屏蔽电荷和均匀电场的作用.     

电场极化条件对石英玻璃的电致二阶非线性光学效应的影响

报道了电场极化条件对石英玻璃的电致二阶非线性光学效应的影响的研究结果。通过实验发现，石英玻璃经较高温度下的电场极化作用所产生的二次谐波发生与极化温度、极化电压具有相关性，并表现出一定的规律性：在一定的极化电压下，二次谐波强度在某一适中的温度下达到极值；在一定的极化温度下，二次谐波强度随极化电压的增大而逐渐增强，并渐趋饱和。根据玻璃的电致二阶非线性极化的“偶极子取向”模型，解释了实验结果。     

光波导结构对其极化电光效应的影响

本文采用热极化技术在掺锗玻璃条形光波导中诱导出非线性光学效应,并通过变化光波导结构改变极化内电场的大小,研究热极化条件对诱导出的电光效应的影响。研究发现在最佳极化时间内,加入薄SiON层的光波导结构经极化后电光效应积累快,相同极化条件下诱导出的电光系数比原有的条形光波导增大约22%,同时极化光波导还存在一个较低的极化阈值电压。实验结果表明加入光波导结构中的薄SiON层可在一定程度上改变极化光波导内的电荷分布,实现强化其内部电场增大光波导内的非线性光学效应或电光效应的目的。     

具有增强介质层电场的SJ-LDMOS

横向超结功率器件遭受衬底辅助耗尽效应,这破坏了超结的电荷平衡,降低了器件的耐压。本文研究了一种基于增强介质层电场的解决方法,以提高横向超结器件（SJ-LDMOS）的耐压。通过高密度的界面电荷增强埋氧层（BOX）的电场从而提高埋氧层的耐压,这可以削弱纵向电场对超结的影响,消除衬底辅助耗尽效应,促进超结电荷平衡。为了获得理想的线性电场增强效果,一种具有槽形埋氧层的超结器件（TBOX SJ-LDMOS）被提出。槽形埋氧层能根据纵向电场的大小自适应地收集空穴,在埋氧层表面形成近似线性的电荷分布,这促进了超结的电荷平衡,提高了SJ-LDMOS器件的耐压,并使其接近理想超结的耐压值。     

光开关玻璃的飞秒光学开关特性

通过在碲玻璃中添加重金属离子,尝试制作了具有较大的非线性折射率、时间响应快、吸收小的光开关玻璃。采用超快飞秒光克尔门技术对光开关玻璃的光克尔信号进行测试,测试结果显示,光开关玻璃的光克尔信号对称性好,信号半高宽度达到~225 fs,三阶非线性极化率达到~0.810-20 m2/V2,透过率达到70%~80%;研制的光开关玻璃为皮秒和飞秒光开光材料的选取提供了依据。     

Simple model for space-charge region capacitance of an exponential-constant p-n junction

Depletion layer properties have been calculated for an exponential-constant p-n junction in silicon by using a simple model. Closed-form expressions are presented for the built-in voltage V/sub bi/ and the offset voltage correction Delta V, respectively, for this junction. These formulas allow the depletion capacitance to be accurately determined from a given value of applied voltage V/sub a/ by manual calculations. The results obtained can readily be extended to other semiconductor materials and other diffused p-n junctions.<>     

An experimental and numerical study on the forward biased SOA ofIGBTs

Thermal and electrical destructions of n-ch 600 V punchthrough type IGBTs in F.B.SOA are investigated by experiments and simulations, The cause of the thermal destruction is the thermal disappearance of built-in potential of p-n junction between the n⁺ emitter and the p base of the IGBT integral DMOSFET occurring at the critical temperature of ~650 K. Experiment and simulation results for the critical temperature show a good agreement. The cause of the electrical destruction is impact ionization at the n^- drift/n⁺ buffer junction in addition to the n^- drift/p base junctions. That triggers a positive feedback mechanism of increasing IGBT integral pnp transistor current which causes the device to lose gate controllability. The experimentally obtained critical power dissipation is ~2000 kW/cm². This value is ten times greater than BJTs. It was also found that emitter ballast resistance (EBR) plays an important role in describing the F.B.SOA of IGBTs     

β辐射伏特效应电池内建电场厚度设计

计算了放射源在半导体中沿厚度方向的能量沉积,并以此计算β辐射伏特效应电池的理想短路电流。通过对比实测短路电流和理想短路电流可以得到β辐射伏特效应电池PN结内建电场的扩散长度。在上述基础上,本文给出了β辐射伏特效应电池内建电场厚度设计原则： 放射源在半导体中能量沉积厚度和PN结内建电场中载流子的扩散长度两者中较小的应作为β伏特效应电池内建电场厚度设计值,如果沉积厚度远远大于载流子扩散长度,则说明多结结构较适合该类β伏特效应电池果,多结的结数应约为沉积厚度与载流子扩散长度的比。     

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.     

STI stress-induced increase in reverse bias junction capacitance

A new contribution to reverse-biased junction capacitance is reported. This component arises from trench isolation stress-induced bandgap narrowing that changes the built-in potential. Experimental junction capacitance measurements show good correlation to simulated oxidation stresses. The reported data agrees well with the predicted values from basic device equations. Stress induced capacitance increase of 12% (7.5%) at 3.3 V reverse bias for p⁺/n (n⁺/ p) junctions, respectively is observed. In addition, well-understood reverse junction leakage relation to stress is also reported. This phenomenon will become increasingly important as trenches become shallower and more tightly spaced     

Surface breakdown in silicon planar junctions—A computer-aided experimental determination of the critical field

Surface breakdown in silicon planar junctions is analysed with emphasis on the evaluation of the critical field (i.e., the maximum electric field within the depletion region at breakdown). This parameter is determined by a computer-aided experimental procedure consisting in relaxation field calculations with boundary conditions governed by junction breakdown voltage (at given gate voltage) as measured on specially processed gate-controlled diodes. The idealization (infinite doping) of the highly doped side of the junction, encountered in previous works, has been eliminated. Values of the critical field determined are in the range of 1 × 10⁶ V/cm (1·0 × 10⁶ V/cm for 1·0 μm gate-oxide and 1·4 × 10⁶ V/cm for 0·3 μm gate-oxide). These values are substantially higher than those estimated by other authors (5–6 × 10⁵ V/cm) and are consistent with independent experimental findings on avalanche (hot-carrier) injection in silicon diodes.     

放射状双pn结抑制片上电感衬底损耗

使用标准CMOS工艺,在放射状的n阱上面扩散p＋,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗．提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度．首次通过接地的p＋扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗．     

放射状双pn结抑制片上电感衬底损耗

使用标准CMOS工艺,在放射状的n阱上面扩散p+,使垂直和水平方向形成双pn结,将此结放在电感的底部用来抑制衬底损耗.提出并实验证明了该结构形成的高阻区厚度不是垂直pn结耗尽层的厚度,而是最低层的pn结的深度.首次通过接地的p+扩散层屏蔽电感到衬底电场,水平和垂直pn结耗尽层厚度随着pn结反向偏压升高改变衬底有效的高阻区厚度,电感品质因数跟随高阻区厚度升降,有效地证明了pn结衬底隔离可以降低电感的衬底电流造成的损耗.