Measurement of transient effects in SOI DRAM/SRAM accesstransistors

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V_DD for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

GaAs dynamic memory design

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns     

A versatile stacked storage capacitor on FLOTOX cell for megabitNVRAM's

A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm ² NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 10⁶ cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM     

Dynamic data retention and implied design criteria forfloating-body SOI DRAM

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications     

A 1.6-GByte/s DRAM with flexible mapping redundancy technique andadditional refresh scheme

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach     

Numerical analysis of alpha-particle-induced soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cell

This paper clarifies alpha-particle-induced soft error mechanisms in floating channel type surrounding gate transistor (FC-SGT) DRAM cells. One FC-SGT DRAM cell consists of an FC-SGT and a three-dimensional (3-D) storage capacitor. The cell itself arranges bit line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F/sup 2/ (F: feature size) per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a major factor to cause soft errors. When an alpha particle penetrates the silicon pillar, generated electrons are collected to the storage node or BL due to the tunneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Consequently, the current flows not only in the surface but also in the entire body region due to the floating body effect. This parasitic bipolar current becomes the largest when an alpha particle penetrates the silicon pillar along the vertical axis. However, in case of FC-SGT DRAM cells, the surrounding gate structure can suppress the floating body effect compared with floating channel type SOI DRAM cells. As a result, the loss of the stored charge in the storage capacitor can be drastically decreased by using FC-SGT DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high-density DRAMs having high soft-error immunity.     

A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme

In order to achieve small self-refresh current (ICC/sub 6/), the first 256-Mb SDRAM with an on-chip thermometer in the DRAM industry is implemented with a new self-refresh scheme. In addition, the biased reference line (BRL) sensing scheme improving refresh characteristics is proposed to increase refresh period and reduce ICC/sub 6/. The on-chip thermometer is characterized by a small area of 0.43 mm/sup 2/, low power consumption with less than 1-/spl mu/A average current, and good accuracy of 5.85/spl deg/C in the worst case. Good accuracy is achieved by incorporating many generic design techniques, including offset-free operational amplifiers and the chopping method, and small area is achieved by applying DRAM cell technology to integrating analog-digital converter. A 75% reduction in ICC/sub 6/ at 60/spl deg/C is achieved with on-chip thermometer and BRL sensing scheme improving 30% of refresh characteristic.     

An 800-MHz embedded DRAM with a concurrent refresh mode

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.     

A novel power-off mode for a battery-backup DRAM

This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage current. By introducing a new word-line power-off/on sequence and a grounded cell plate technique, all cell data are maintained after power source is turned off and on. Although the proposed mode requires a power-on current, an average standby leakage current is reduced by a factor of 1000, and the total standby current including both the leakage current and refresh current is reduced by a factor of 10 in a 1 Gb DRAM. The proposed circuit technique was verified by a 64 Kb DRAM test chip. All cell data were successfully maintained after the power source switching. The measured power-off time was as long as the measured data retention time in the conventional DRAM standby mode     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells     

Trends in megabit DRAM circuit design

The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, and speed. The memory cell signal charge has decreased gradually with an increase in memory cell size, despite the vertically structured cell designs. To offset this decrease, multidivided data-line structures, low-power design, and transposition of folded data lines are essential. To reduce power dissipation, an increase in the maximum refresh cycle and multidivided data lines combined with shared I/O in addition to a reduced operating voltage are efficient. A BiCMOS circuit provides a high-speed access time with low cost due to the high drivability of the driver and high sensitivity of the amplifier. It is predicted that the current DRAM technology might be diversified in the future so that a large-memory-capacity-oriented technology would coexist with a high-speed-oriented technology, posing power-supply standardization as a continuing serious concern     

Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.     

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm². We designed a 1Mb DRAM with an open bit‐line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V_cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.     

Determination of interface trap capture cross sections usingthree-level charge pumping

A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO₂ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I_cp to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET     

A new simplified charge pumping current model and its modelparameter extraction [MOSFET]

Using the Shockley-Read-Hall (SRH) theory, a simple analytic charge pumping current model has been developed and its accuracy verified by exact numerical analysis. It is shown that the derived analytic charge pumping current model with constant capture cross sections for electrons and holes does not correctly simulate the rising (falling) edges of the experimental charge pumping current. According to the slopes of the logarithmic charge pumping current, effective capture-cross-section models for elections and holes are proposed and are incorporated into the developed analytic charge pumping current model. It is shown that the experimental charge pumping current can be simulated very well by using the modified analytic model     

一种交错并行隐式刷新增益单元eDRAM设计

设计了一种与逻辑工艺兼容的64 kb高速高密度嵌入式增益单元动态随机存储器(eDRAM)。该存储器单元通过结构和版图的优化,典型尺寸为同代SRAM的40%。高低阈值管的引入分别改善了单元的读取速度和数据保持时间。同时交错并行隐式刷新机制利用增益存储单元读、写端口独立的结构和操作特性,配以合适的时序和仲裁机制,使得在无额外通信信号和握手接口下,实现刷新与访问互不影响,数据访问率达到100%。相比其他隐式刷新技术,该技术不需要过大的外围开销即可完成访问带宽加倍。芯片用SMIC 0.13μm CMOS工艺实现,大小为1.35 mm×1.35 mm。     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.