HfO2高K栅介质薄膜的电学特性研究

研究了高 K(高介电常数 )栅介质 Hf O2 薄膜的制备工艺 ,制备了有效氧化层厚度为 2 .9nm的超薄MOS电容。对电容的电学特性如 C-V特性 ,I-V特性 ,击穿特性进行了测试。实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。因此 ,Hf O2 栅介质可能成为 Si O2 栅介质的替代物。     

恒电流应力引起HfO_2栅介质薄膜的击穿特性

利用磁控溅射的方法在p- Si上制备了高k(高介电常数)栅介质Hf O2薄膜的MOS电容,对薄栅氧化层电容的软击穿和硬击穿特性进行了实验研究.利用在栅极加恒电流应力的方法研究了不同面积Hf O2 薄栅介质的击穿特性以及击穿对栅介质的I- V特性和C- V特性的影响.实验结果表明薄栅介质的击穿过程中有很明显的软击穿现象发生,与栅氧化层面积有很大的关系,面积大的电容比较容易发生击穿.分析比较了软击穿和硬击穿的区别,并利用统计分析模型对薄栅介质的击穿机理进行了解释     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

N_2和NH_3退火对铪铝氧栅介质C-V特性的影响

采用原子层淀积(ALD)的方法在Si(100)衬底上制备了铪铝氧(HfAlO)高介电常数介质,并研究了N2和NH3退火对于介质薄膜的影响。改变原子层淀积的工艺,制备了三组含有不同Al∶Hf原子比的铪铝氧(HfAlO)高介电常数介质。电容电压特性(C-V)测试表明,薄膜的积累电容密度随着薄膜中Al∶Hf原子比的减少而增加。实验表明,用N2和NH3对样品进行淀积后退火,可以减小等效电容厚度(CET)、降低固定正电荷密度以及减小滞回电压,从而有效地提高了介质薄膜的电学特性。     

四方晶相HfO2电子结构和光学性质研究

采用密度泛函理论(DFT)框架下的局域密度近似(LDA),计算了四方HfO2晶体的电子结构,包括能带结构和态密度.在此基础上计算了四方Hf02晶体的光学线性响应函数,包括复介电函数、吸收光谱、复折射率和光电导谱.通过比较发现,计算结果与实验结果吻合较好,说明采用密度泛函理论的局域密度近似来计算HfO2材料的光学性质是比较可靠的.     

ULSI制备中铈在SiO2介质CMP抛光中的作用研究

对ULSI制备中铈(Ce)在Si02介质的CMP中的应用及对Ce胶体抛光液的制备进行了较为深入的实验研究,并对提高抛光效果进行了大量实验.     

溶液法制备金属氧化物薄膜晶体管的研究进展

金属氧化物薄膜晶体管(MOTFT)因具有迁移率高、可见光透明、工艺简单、可低温制备等优势,在高性能平板显示、可穿戴柔性电子、集成传感器等领域具有广阔的应用前景.主要回顾了溶液法制备MOTFT的研究进展.首先介绍了溶液法制备MOTFT相对于其他方法的优势,如工艺简单、制作成本低、易掺杂;然后阐述了浸涂法、喷雾法、旋涂法、印刷法加工工艺的特点及优缺点,比较了不同溶液加工工艺所制备MOTFT的电学性能;最后指出了目前溶液法制备MOTFT存在的问题,并从有源层材料与结构、栅介质层材料与界面、退火与预处理3个方面详细地讨论了溶液法制备的优化方法.     

TaON界面层Hf基高κ栅介质Ge MOS电容特性研究

制备了含TaON界面层的Hf基氧化物和氮氧化物叠层高κ栅介质GeMOS电容。器件的测量结果表明,HfTaON/TaON叠层栅介质GeMOS电容表现出良好的界面特性、低的栅极漏电流密度、小的等效氧化物厚度(0.94nm)、高的介电常数(～24)和良好的可靠性。这些都归因于TaON界面层阻挡了O及金属原子向Ge衬底的扩散,抑制了不稳定的低κGeOx的生长,从而改善界面质量,增强器件性能。     

基于降低有机场效应晶体管泄漏电流的研究进展

近年来,由于有机场效应晶体管(OFET)具有成本低、机械柔性优异且可大面积制备等优点成为国际研究的前沿领域之一.迄今为止,OFET的载流子迁移率已超过了非晶硅薄膜晶体管,在柔性集成电路中表现出了巨大的应用潜力.随着技术的不断改进,OFET的工作频率不断提高.首先阐述了泄漏电流的来源;然后介绍了影响OFET静态功耗的最主要因素是栅极泄漏电流,总结了近年来降低OFET栅极泄漏电流的主要方法,如构建多层结构的栅介质、开发新型栅介质材料和交联栅介质材料;最后对降低OFET泄漏电流的方法进行了展望.     

基于FET结构的MoS2器件的研究进展

对带隙可调的二维层状半导体二硫化钼(MoS2)的材料特性以及基于MoS2薄膜的器件性能和应用进行了简单阐述,重点分析了多种MoS2场效应晶体管(FET)的结构特点,并对MoS2 FET的制备工艺、电学性能(载流子迁移率、电流开关比、亚阈值摆幅等)以及栅极介质层材料对器件性能的影响等进行了综述.在此基础上进一步总结了近年...     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

A novel self-aligned offset-gated polysilicon TFT using high-/spl kappa/ dielectric spacers

In this letter, a novel self-aligned offset-gated Poly-Si thin-film transistor (TFT) using high-/spl kappa/ dielectric Hafnium oxide (HfO/sub 2/) spacers is proposed and demonstrated. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. The permittivity of the deposited HfO/sub 2/ is approximately 20. Experimental results show that with the high vertical field induced underneath the high-/spl kappa/ spacers, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, compared to the conventional lightly doped drain or oxide spacer TFTs. The on-state current in the offset-gated Poly-Si TFT using the HfO/sub 2/ spacers is approximately two times higher than that of the conventional oxide spacer TFT.     

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy/sub 2/O/sub 3/-incorporated HfO/sub 2/ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy/sub 2/O/sub 3/ laminated HfO/sub 2/ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO/sub 2/. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy/sub 2/O/sub 3//HfO/sub 2/ multimetal stack oxide n-MOSFET such as lower V/sub T/, higher drive current, and an improved channel electron mobility are reported. Dy/sub 2/O/sub 3//HfO/sub 2/ sample also shows a better immunity for V/sub t/ instability and less severe charge trapping characteristics. Two different rationed Dy/sub 2/O/sub 3//HfO/sub 2/ and HfO/sub 2/ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D/sub it/), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility.     

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.     

高k HfO2栅介质淀积后退火工艺研究

研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求.     

Diffusion coefficient of B in HfO/sub 2/

We implanted B ions in a 110-nm-thick HfO/sub 2/ layer, subjected the substrates to various thermal processes, and evaluated the diffusion coefficient by comparing experimental and numerical data. We found that the diffusion coefficient of B in HfO/sub 2/ is higher than that in SiO/sub 2/ by about four orders and almost the same as that in Si. Therefore, the penetration of B through this layer can be expected to be significant, making the use of a cover layer indispensable for p/sup +/ polycrystalline silicon gate devices.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.