A Novel Bandpass Filter Based on Current Feedback Amplifier

An application demonstrating some advantages of the current feedback amplifier (CFA) over the voltage op-amp counterpart is given. A novel bandpass filter achieving a high quality factor and variable gain based on a single CFA is proposed. It is shown that unlike the op-amp Sallen-Key bandpass filter, the CFA filter is more suitable for high frequency applications. Hussain A. Alzaher was born in Qatif-Alawamia, Saudi Arabia, in 1972. He received the B.S. and M.S. degrees (with honors) in electrical engineering from King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi Arabia, in 1994 and 1997, respectively, and the Ph.D. degree from The Ohio State University, Columbus, in 2001. Since 1994, he has been with KFUPM as a faculty member in the electrical engineering department. His research interest includes applications of electronic circuit techniques for wireless communications: Multi-standard mobile phones, Bluetooth, WLAN and WiMAX. Dr. Alzaher is the recipient of the 1994/1995 Prince Muhammed bin Fahd bin Abdulaziz Award for Excellence in Scientific Achievement. He is also the recipient of the 2003 Showman award for Young Arab Researchers, Engineering Science.     

Adaptive Chip-Level Channel Estimation for IMT-DS System: DL and UL

In this paper, chip-level adaptive channel estimation has been explored by using LMS algorithm for wideband CDMA channel estimation. The expression for the optimum step-size is modified for fading channel estimation problem. In addition, a new method is proposed to obtain channel estimates with known pilot symbols which is found to give better results than other methods. For slow fading channels, like pedestrian channel, LMS estimator with no update mode is found to give satisfactory results. For fast fading channels, like vehicular channel, a common decision directed technique of channel estimation is modified to be used at chip-level in the downlink (DL). A novel despreader-respreader based channel estimator has been proposed to obtain uplink channel estimates at chip level which resolves the deficiencies of conventional methods. The performance of Rake receiver with proposed channel estimation schemes for IMT-DS system – a 3G mobile communication standard – is evaluated in terms of BER. S. Faisal A. Shah received the B.S. degree from NED University of Engineering and Technology, Karachi, Pakistan, in 1998 and the M.S. degree from King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, in 2001, both in Electrical Engineering. From 2001 to 2004, he was a Lecturer in Electrical & Electronics Engineering Department, University of Sharjah, UAE. In September 2004, he joined the Electrical and Computer Engineering Department of University of Minnesota, USA, as a research assistant where he is currently pursuing the Ph.D. degree in Electrical Engineering. His research interests include ultra-wideband communication systems, adaptive signal processing and its application to wireless communication systems. Asrar U.H. Sheikh graduated from the University of Engineering and Technology, Lahore, Pakistan with first class honours and received his M.Sc. and Ph.D. degrees from the University of Birmingham, England, in 1966 and 1969 respectively. After completing teaching assignments in several countries, he returned to Birmingham as a Research Fellow in 1975. He worked at Carleton University from 1981 to 1997, first as Associate Professor and later as a Professor and Associate Chairman for Graduate Studies. He was the Founder Director of PCS Research Laboratory at Carleton University. Before taking position of Bugshan/Bell Lab Chair in Telecommunications at King Fahd University of Petroleum and Minerals in April 2000, he was a Professor and Associate Head of the Department of Electronic and Information Engineering at Hong Kong Polytechnic University, where he was founding director of Wireless Information Systems Research (WISR) Centre. At KFUPM he established Telecommunications Research Laboratory. Professor Sheikh is the author of a recently published book, Wireless Communications - Theory & Techniques published by Kluwer Academic Publishers, Orwell, Mass., USA. He has published over 230 papers in international journals and conference proceedings. He also authored or co-authored 30 technical reports. Dr. Sheikh is a co-recipient of Paul Adorian Premium from IERE (London) for his work on impulsive noise characterization. He was awarded teaching achievement awards in 1984 and 1986, and Research Achievement Award in 1994, all by Carleton University. Dr. Sheikh is actively involved in several international conferences mainly as a member of Technical Program Committees. He has organized and chaired many technical sessions at several international conferences. He Chaired the Technical Program of VTC'98. He is an editor of IEEE Transaction on Wireless Communications, a Technical Associate Editor of IEEE Communication Magazine. He is on the Editorial Board of Wireless Personal Communications, and Wireless Communications and Mobile Computing. He was a co-guest editor of the Special Issue of WPC on Interference. Dr. Sheikh is also on the reviewer panels of many IEEE and IEE Transactions and Journals. Dr. Sheikh has been consultant to many private companies and government agencies. His current interests are in signal processing in communications, mitigation of interference, spread spectrum and 3G and beyond systems. His other interests include helping developing countries in education and research. He had assignments under UNDP's sustained Development Program. He is a Fellow of the IEEE and a Fellow of the IEE. Dr. Sheikh is listed in Marquis Who's Whos in the world and Who's Who in Science and Engineering.     

New 1.5-V CMOS second generation current conveyor based on wide range transconductor

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed CCII+ uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel and p-channel), to realize the input stage. This solution allows almost a rail-to-rail input and output operation; also it reduces the number of current mirrors needed in the input stage. The CCII+ is operating at supply voltages of ±0.75 V with a total standby current of 133 μA. The application of the proposed CCII+ to realize a MOS-C second order maximally flat low-pass filter is given. PSpice simulation results for the proposed CCII+ and its application are given. Ahmed H. Madian was born in Jeddah, Saudi Arabia in 1975. He received the B.Sc. degree with honors, and the M.Sc. degree in electronics and communications from Cairo University, Cairo, Egypt, in 1997, and 2001 respectively. He is currently a Research Assistant in the Electronics Engineering Department, Micro-Electronics Design Center, Egyptian Atomic Energy Authority, Cairo, Egypt. His research interests are in circuit theory; low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed/digital applications on filed programmable gate arrays. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the BSc degree with honors in 1994, the MSc degree in 1996, and the PhD degree in 1999, all from the Electronics and Communications Department, Cairo University, Egypt. He is currently an Associate Professor at the Electrical Engineering Department, Fayoum University, Egypt. He is currently also a visiting Associate Professor at the Electrical and Electronics Engineering Department, German University in Cairo, Egypt. In 2005, He was decorated with the Science Prize in Advanced Engineering Technology from the Academy of Scientific Research and technology. His research and teaching interests are in circuit theory, fully-integrated analog filters, high-frequency transconductance amplifiers, low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964,the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997-September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985-1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987-1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr Soliman gave a lecture at Nanyang Technological University, Singapore.Dr Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004-Now.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

Moving mainframe VM users to a distributed UNIX system (KFUPM VM rightsizing experience)

Migration from one platform to another is a mammoth task. This article describes the experiences of King Fahd University of Petroleum and Minerals in moving from VM/CMS to UNIX, detailing the reasons for making this change, the problems encountered and drawing practical conclusions that would facilitate such a process. © 1997 John Wiley & Sons, Ltd.     

A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 Ω. The opamp provides a maximum output swing of 700 μA, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering.He is currently Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer, 1985) and with the Technical University of Wien, Austria (Summer, 1987).In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

Theoretical Analysis and Performance of NC-PRMA Protocol for Multichannel Wireless Networks

In this paper, we analyze the effect of duplexing schemes on the throughput and the average packet dropping probability of a new multichannel wireless access protocol which allows for non-collision packet reservation multiple access with multiple channel (NC-PRMA/MC). N _C equal-capacity, orthogonal, traffic channels are shared by M mobile users on the uplink. Transmission attempts on the uplink are made by using time-frequency signaling in every frame, which enables transmission attempts of mobile users to be conveyed to the base station without collisions. Two kinds of duplexing schemes, frequency division duplexing and shared time division duplexing, are considered in the performance analysis. Using a discrete-time Markov chain analysis, we derive the analytic expressions for the average per channel throughput and the average packet dropping probability. Computer simulation results verify the analysis. Analytical evaluation and computer simulation show that NC-PRMA/MC with shared time division duplexing improves the channel capacity, which approaches the theoretical upper bound. Jenn-Kaie Lain born in Taiwan, R.O.C., in 1973. He received the B.E. degree in engineering science from the National Cheng Kung University, Tainan, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from the National Chung Cheng University, Chiayi, R.O.C., in 1995 and 2001, respectively. Since August 2001, he joined the faculty of Department of Computer Science and Information Engineering at Shu-Te University, Kaohsiung, Taiwan, R.O.C., as an Assistant Professor. He has been on the Faculty at National Yunlin University of Science and Technology, Yunlin, Taiwan, R.O.C., since August 2002 and currently holds the position of Assistant Professor in the Institute of Electronic and Information Engineering. His current research interest is in the field of coding and modulation as well as efficient receiver designs for broadband wireless communications. Jyh-HorngWen received his B.S. degree in Electronic Engineering from the National Chiao Tung University, Hsing-Chu, Taiwan, in 1979 and the Ph.D. degree in Electrical Engineering from the National Taiwan University, Taipei, in 1990. From 1981 to 1983, he was a Research Assistant with the Telecommunication Laboratory, Ministry of Transportation and Communications, Chung-Li, Taiwan. From 1983 to 1991, he was a Research Assistant with the Institute of Nuclear Energy Research, Taoyun, Taiwan. Since February 1991, he has been with the Institute of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, first as an Associate Professor and, since 2000, as a Professor. He was also the Managing Director of the Center for Telecommunication Research, National Chung Cheng University, from Aug. 2000 to July 2004. Currently, he is also the Dean of General Affairs, National Chi Nan University. He is an Associate Editor of the Journal of the Chinese Grey System Association. His current research interests include computer communication networks, cellular mobile communications, personal communications, spread-spectrum techniques, wireless broadband systems, and gray theory. Prof.Wen is a member of the IEEE Communication Society, the IEEE Vehicular Technology Society, the International Association of Science and Technology for Development,the Chinese Grey System Association, and the Chinese Institute of Electrical Engineering.     

A secure authentication and billing architecture for wireless mesh networks

Wireless mesh networks (WMNs) are gaining growing interest as a promising technology for ubiquitous high-speed network access. While much effort has been made to address issues at physical, data link, and network layers, little attention has been paid to the security aspect central to the realistic deployment of WMNs. We propose UPASS, the first known secure authentication and billing architecture for large-scale WMNs. UPASS features a novel user-broker-operator trust model built upon the conventional certificate-based cryptography and the emerging ID-based cryptography. Based on the trust model, each user is furnished with a universal pass whereby to realize seamless roaming across WMN domains and get ubiquitous network access. In UPASS, the incontestable billing of mobile users is fulfilled through a lightweight realtime micropayment protocol built on the combination of digital signature and one-way hash-chain techniques. Compared to conventional solutions relying on a home-foreign-domain concept, UPASS eliminates the need for establishing bilateral roaming agreements and having realtime interactions between potentially numerous WMN operators. Our UPASS is shown to be secure and lightweight, and thus can be a practical and effective solution for future large-scale WMNs. Yanchao Zhang received the B.E. degree in Computer Communications from Nanjing University of Posts and Telecommunications, Nanjing, China, in July 1999, and the M.E. degree in Computer Applications from Beijing University of Posts and Telecommunications, Beijing, China, in April 2002. Since September 2002, he has been working towards the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, Florida, USA. His research interests are network and distributed system security, wireless networking, and mobile computing, with emphasis on mobile ad hoc networks, wireless sensor networks, wireless mesh networks, and heterogeneous wired/wireless networks. Yuguang Fang received the BS and MS degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D degree in Systems and Control Engineering from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D degree in Electrical Engineering from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997. From 1987 to 1988, he held research and teaching position in both Department of Mathematics and the Institute of Automation at Qufu Normal University. From September 1989 to December 1993, he was a teaching/research assistant in Department of Systems, Control and Industrial Engineering at Case Western Reserve University, where he held a research associate position from January 1994 to May 1994. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From September 1995 to May 1997, he was a research assistant in Department of Electrical and Computer Engineering at Boston University. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. In May 2000, he joined the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he got early promotion to Associate Professor with tenure in August 2003, and to Full Professor in August 2005. His research interests span many areas including wireless networks, mobile computing, mobile communications, wireless security, automatic control, and neural networks. He has published over one hundred and fifty (150) papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He also received the 2001 CAST Academic Award. He is listed in Marquis Who’s Who in Science and Engineering, Who’s Who in America and Who’s Who in World. Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for IEEE Transactions on Mobile Computing, an Editor for ACM Wireless Networks, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications: Wireless Communications Series, an Area Editor for ACM Mobile Computing and Communications Review, an Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and Feature Editor for Scanning the Literature in IEEE Personal Communications. He has also actively involved with many professional conferences such as ACM MobiCom’02 (Committee Co-Chair for Student Travel Award), MobiCom’01, IEEE INFOCOM’06, INFOCOM’05 (Vice-Chair for Technical Program Committee), INFOCOM’04, INFOCOM’03, INFOCOM’00, INFOCOM’98, IEEE WCNC’04, WCNC’02, WCNC’00 (Technical Program Vice-Chair), WCNC’99, IEEE Globecom’04 (Symposium Co-Chair), Globecom’02, and International Conference on Computer Communications and Networking (IC3N) (Technical Program Vice-Chair).     

Extremely-Wide-Range Supply-Independent CMOS Voltage References for Telemetry-Powering Applications

This paper reports a voltage reference circuit in standard CMOS process. It exhibits excellent supply independency for a wide input voltage range, which is of great importance in telemetry-powered systems. This circuit is based on the well-known V_GS-reference supply-independent current reference circuit, but it is designed to serve as a voltage reference. While the reference current generated by this circuit varies with the supply voltage, a self-compensating mechanism can be found in voltage-mode operation of the circuit that results in a supply-independent reference voltage. This supply independency is well observed in the static operation of the circuit over an extremely wide input range, as well as in its dynamic behavior for high frequency ripples on the input voltage. Based on the proposed idea, a multi-output voltage reference and a CMOS DC level shifter are also designed. The proposed voltage reference circuits have been fabricated using MOSIS 1.6 μm standard CMOS process. The basic voltage reference provides 957 μV/V static supply dependency, rejects input ripples of up to 8 MHz by 60± 3dB, and consumes only 15.8–36.9 μA when the input voltage varies in the range 2.6–12 V. Amir M. Sodagar received the B.S. degree from K.N. Toosi (KNT) University of Technology, Tehran, Iran, and M.S. and Ph.D. degrees from Iran University of Science & Technology (IUST), Tehran, Iran all in Electrical Engineering in 1992, 1995, and 2000, respectively. From 1992 to 2000 he was with S. Rajaee University as a Lecturer. After receiving the Ph.D. degree until 2002 he was with the NSF Engineering Research Center for Wireless Integrated Micro Systems (WIMS), Electrical Engineering & Computer Science (EECS) Dept., University of Michigan as a Post-Doctoral Research Fellow. From 2002 to 2004 he was with S. Rajaee University and KNT University of Technology as an Assistant Professor and an Adjunct Professor, respectively, and since 2004 he has been with the University of Michigan as an Associate Visiting Research Scientist. Dr. Sodagar was known as the Outstanding Electrical Engineering Graduate Student of the IUST in 1995, and receiv ed the IUST's Best Ph.D. Research Achievement Award in 2000. He was also the recipient of S. Rajaee University's Distinguished Faculty Member Award for “1998–1999” and “1999–2000” academic years, and S. Rajaee University's Distinguished Researcher Award for “2002–2003” academic year. He was involved in the design of integrated circuits in collaboration with the Center for Semiconductor Research and Fabrication from 1994 to 1995, VLSI Circuits & Systems Laboratory at the University of Tehran from 1997 to 1998, and EMAD Semicon Company from 1998 to 2000. He has authored one book, authored/co-authored more than 20 journal and conference papers, and served as the technical paper reviewer for several IEEE journals/transactions and also conferences. Dr. Sodagar's research interests are generally in the field of mixed-signal integrated circuit design, and focused on: integrated circuits for neural recording & stimulation, telemetry powering and control of implantable microsystems, frequency synthesizers, analog building blocks, and transistor-level implementations of digital logic families. Khalil Najafi (IEEE S '84, M '86, SM '97, F'00) received the B.S., M.S., and the Ph.D. degree in 1980, 1981, and 1986 respectively, all in Electrical Engineering from the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. From 1986–1988 he was employed as a Research Fellow, from 1988–1990 as an Assistant Research Scientist, from 1990–1993 as an Assistant Professor, from 1993–1998 as an Associate Professor, and since September 1998 as a Professor and the Director of the Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan. His research interests include: micromachining technologies, micromachined sensors, actuators, and MEMS; analog integrated circuits; implantable biomedical microsystems; micropackaging; and low-power wireless sensing/actuating systems. Dr. Najafi was awarded a National Science Foundation Young Investigator Award from 1992–1997, was the recipient of the Beatrice Winner Award for Editorial Excellence at the 1986 International Solid-State Circuits Conference, of the Paul Rappaport Award for co-authoring the Best Paper published in the IEEE Transactions on Electron Devices, and of the Best Paper Award at ISSCC 1999. In 2003 he received the EECS Outstanding Achievement Award, in 2001 he received the Faculty recognition Award, and in 1994 the University of Michigan's “Henry Russel Award” for outstanding achievement and scholarship, and was selected as the “Professor of the Year” in 1993. In 1998 he was named the Arhtur F. Thurnau Professor for outstanding contributions to teaching and research, and received the College of Engineering's Research Excellence Award. He has been active in the field of solid-state sensors and actuators for more than twenty years, and has been involved in several conferences and workshops dealing with solid-state sensors and actuators, including the International Conference on Solid-State Sensors and Actuators, the Hilton-Head Solid-State Sensors and Actuators Workshop, and the IEEE/ASME Micro Electromechanical Systems (MEMS) Conference. Dr. Najafi is the Editor for Solid-State Sensors for IEEE Transactions on Electron Devices, an Associate Editor for the Journal of Micromechanics and Microengineering, Institute of Physics Publishing, and an editor for the Journal of Sensors and Materials. He also served as the Associate Editor for IEEE Journal of Solid-State Circuits from 2000–2004, and the associate editor for IEEE Trans. Biomedical Engineering from 1999–2000. He is a Fellow of the IEEE.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Programmable CNN Analogue Chip for RD-PDE Multi-Method Simulations

Cellular Non Linear Networks can be useful applied for the solution of several types of Partial Differential Equations (PDEs). This paper will describe an analogue circuit implementation for the simulation of one-dimensional Reaction-Diffusion PDE with the possibility to set different boundary conditions as well as to select different discretization methodologies. Fausto Sargeni was born in Riano (ROMA) in 1961. He received the Dipl. Eng. degree in Electronic Engineering at the University of Rome “La Sapienza" in 1987. In 1989 he jointed the Dept. of Electronic Engineering at the University of Rome “Tor Vergata" as Assistant Professor. In 1998 he became Associate Professor. His research interests include analog VLSI circuits for non linear circuits and high-speed interconnections. Vincenzo Bonaiuto was born in Rome, Italy, in 1962. He received the Dipl. Eng. degree in Electronic Engineering at the University of Rome “La Sapienza". In 1997 he received the the Ph.D. in Telecommunication and Microelectronics. In 1996 he jointed the Electronic Engineering Dept. as Assistant Professor at the University of Rome “Tor Vergata” and, in 2002, he became Associate Professor. His main research interests are in the area of non linear circuits, Artificial Neural Networks analogue/digital VLSI circuits implementation.     

High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation

In this paper we propose novel high-speed and low-power architecture for the context formation sub-block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 test images, each one 512*512 pixels, gray scale with 8 bit pixels. The proposed architecture incorporates a check unit to detect unnecessary operations in both pass1 and pass2 of the EBCOT block. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture reduces the power consumption about 20.64% and increases the processing speed to about 33.67% with respect to the speedy reference architecture. The proposed architecture has a processing speed close to the parallel mode architectures with almost the same area for serial mode architectures and more power saving. The proposed architecture gathers the basic advantages of the serial and parallel mode implementations in addition to lower power consumption. Ramy E. Aly received the B.S. degree in electrical engineering from University of Alexandria, Egypt, in 1994, and the M.S. degree in electrical engineering from Old Dominion University, VA, in 2001 and M.S. in computer engineering from University of Louisiana at Lafayette, in 2002. He is currently working toward his Ph.D. degree at the Center for Advanced Computer Studies (CACS), University of Louisiana, Lafayette. Since 2001, he has been a Research Assistant with the CACS, in the VLSI Research group of M. A. Bayoumi, University of Louisiana. His research interests include low-power VLSI circuit design, low-power SRAM design, JPEG2000 Architecture and CAD-tools. Magdy A. Bayoumi(S'80-M'84-SM'87-F'99) received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a Faculty Member since 1985. He has edited and coedited three books in the area of VLSI Signal Processing. He has one patent pending. His research interests include VLSI design methods and architectures, low-power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wide-band network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for technical activities of the IEEE Circuits and Systems Society. He was the Cochairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a Member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a Member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a Member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

Pipeline of Successive Approximation Converters with Optimum Power Merit Factor

In this paper, we present a low power 12 bit 5 MSPS, successive approximation converter architecture using pipeline technique. The converter consumes 4 mW at the Nyquist rate input with 1.8 V power supply. By combination of pipeline and successive architecture, the entire circuit, simulated at the transistor level in a 0.18 μ CMOS process, achieves a FoM (Figure of Merit) of 0.19 pJ/conversion. Jinghua Li was born in 1973. He received the MSEE and BSEE Degree from College of Electronics and information, Shanghai Jiaotong University and Harbin Engineering University in 1997 and 1994 respectively. He is currently pursuing Ph.D degree in Department of Electrical Engineering, Texas A&M University, College Station, TX, USA. In 1997, he joined Bell Laboratory (China), Lucent Technologies as a member of technical staff. He worked on single-chip HDTV decoder IC and Sonet/SDH SoC for various projects in Murray Hill, NJ, USA and Shanghai China. He also finished projects on hardware implementation of Video conference/Phone based on H.263 standard as his master thesis. Since 2000, he has been a research assistant in Analog Mixed Signal center, TAMU. Most currently his research interests are focused on low power analog to digital conversion IC design, CMOS implementation of 10 G/2.5 G clock data recovery IC for high speed serial communications. Franco Maloberti received the Laurea Degree in Physics (Summa cum Laude) from the University of Parma, Parma Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico in 1996. In 1993 he was a Visiting Professor at ETH-PEL, Zurich. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group University of Pavia, Pavia, Italy and the TI/J.Kilby Analog Engineering Chair Professor at the Texas A&M University. He is currently the Distinguished Microelectronic Chair Professor at University of Texas at Dallas and part-time Professor at the University of Pavia, Italy. His professional expertise is in the design, analysis and characterization of integrated circuits and analogue digital applications, mainly in the areas of switched capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analogue and mixed A-D design. He has written more than 250 published papers, three books and holds 15 patents. He was in 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institute of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS Triode Transistor Transconductor for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects' Evaluator, Reviewer and as European Union expert in many European Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs' evaluations. Dr. Maloberti was Vice-President, Region 8, of the IEEE Circuit and Systems Society from 1995 to 1997 and an Associate Editor of IEEE-Transaction on Circuit and System-II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. He is the President of the IEEE Sensor Council and member of the Board of Governors of the IEEE CAS Society. He is a member of the Italian Electrothecnical and Electronic Society (AEI), the Editorial Board of Analog Integrated Circuits and Signal Processing, and Fellow of IEEE.     

HISNs: Distributed gateways for application-level integration of heterogeneous wireless networks

Integration of different kinds of wireless networks to provide people seamless and continuous network access services is a major issue in the B3G network. In this paper, we propose and implement a novel Heterogeneous network Integration Support Node design (HISN) and a distributed HISN network architecture for the integration of heterogeneous networks, under which the Session Mobility, Personal Mobility, and Terminal Mobility for mobile users can be maintained through the Session Management mechanism. Thus, the HISN node can serve as an agent for the user to access Internet services independent of underlying communication infrastructure. Our design is transparent to the bearer networks and the deployment of the HISN network does not need to involve the operators of the heterogeneous wireless networks. This paper is an extension of the work that won the championship of the Mobile Hero contest sponsored by Industrial Development Bureau of Ministry of Economic Affairs, Taiwan, R.O.C., and was awarded USD 30,000. The work of Lin, Chang and Cheng was supported in part by the National Science Council (NSC), R.O.C, under the contract number NSC94-2213-E-002-083 and NSC94-2213-E-002-090, and NSC 94-2627-E-002-001, Ministry of Economic Affairs (MOEA), R.O.C., under contract number 93-EC-17-A-05-S1-0017, the Computer and Communications Researches Labs/Industrial Technology Research Institute (CCL/ITRL), Chunghwa Telecom Labs, Telcordia Applied Research Center, Taiwan Network Information Center (TWNIC), and Microsoft Corporation, Taiwan. The work of Fang was supported in part by the US National Science Foundation Faculty Early Career Development Award under grant ANI-0093241 and US National Science Foundation under grant DBI-0529012. Phone Lin (M’02-SM’06) received his BSCSIE degree and Ph.D. degree from National Chiao Tung University, Taiwan, R.O.C. in 1996 and 2001, respectively. From August 2001 to July 2004, he was an Assistant Professor in Department of Computer Science and Information Engineering (CSIE), National Taiwan University, R.O.C. Since August 2004, he has been an Associate Professor in Department of CSIE and Graduate Institute of Networking and Multimedia, National Taiwan University, R.O.C. His current research interests include personal communications services, wireless Internet, and performance modeling. Dr. Lin is an Associate Editor for IEEE Transactions on Vehicular Technology, a Guest Editor for IEEE Wireless Communications special issue on Mobility and Resource Management, and a Guest Editor for ACM/Springer MONET special issue on Wireless Broad Access. He is also an Associate Editorial Member for the WCMC Journal. P. Lin’s email and website addresses are plin@csie.ntu.edu.tw and http://www.csie.ntu.edu.tw/∼plin, respectively. Huan-Ming Chang received the BSCSIE degree and Master CSIE degree from National Taiwan University, R.O.C. in 2003 and 2005, respectively. His current research interest includes wireless Internet. H.-M. Chang’s email address is r91114@csie.ntu.edu.tw. Yuguang Fang received a Ph.D. degree in Systems and Control Engineering from Case Western Reserve University in January 1994, and a Ph.D. degree in Electrical Engineering from Boston University in May 1997. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology. In May 2000, he joined the Department of Electrical and Computer Engineering at University of Florida where he got the early promotion to Associate Professor with tenure in August 2003 and to Full Professor in August 2005. He has published over 180 papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He is currently serving as an Editor for many journals including IEEE Transactions on Communications, IEEE Transactions on Wireless Communications, IEEE Transactions on Mobile Computing, and ACM Wireless Networks. He is also actively participating in conference organization such as the Program Vice-Chair for IEEE INFOCOM’2005, Program Co-Chair for the Global Internet and Next Generation Networks Symposium in IEEE Globecom’2004 and the Program Vice Chair for 2000 IEEE Wireless Communications and Networking Conference (WCNC’2000). Shin-Ming Cheng received the BSCSIE degree in 2000 from National Taiwan University, Taiwan, R.O.C., where he is currently working toward the Ph.D. degree in the Department of Computer Science and Information Engineering, National Taiwan University. His current research interests include mobile computing, personal communications services, and wireless Internet. S.-M. Cheng’s email and website addresses are shimi@pcs.csie.ntu.edu.tw and http://www.pcs.csie.ntu.edu.tw/∼shimi, respectively.     

Strongly Consistent Access Algorithms for Wireless Data Networks

In wireless data networks such as the WAP systems, the cached data may be time-sensitive and strong consistency must be maintained (i.e., the data presented to the user at the WAP handset must be the same as that in the origin server). In this paper, we study the cached data access algorithms in such systems. Two caching algorithms are investigated. In Algorithm I, Pull-Each-Read, whenever a data access occurs, the client always asks the server whether the cached entry in the client is valid or not. In Algorithm II, Callback, the server always invalidates the cached entry in the client whenever an update occurs. Analytic models are proposed to evaluate the performance of these algorithms. Our studies show that Algorithm II outperforms Algorithm I if the data access rate is high and the access pattern is irregular. We also design an adaptive mechanism to effectively switch between the two algorithms to take advantages of both algorithms. We also apply the single-level cached data access algorithms for the multi-level cache hierarchy. Our study indicates that with appropriate arrangement, strongly consistent cached data access for wireless Internet (such as WAP) can be efficiently supported.Yuguang Fang received the B.S. and M.S. degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D degree from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D degree from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997.From 1987 to 1988, he held research and teaching positions in both Department of Mathematics and the Institute of Automation at Qufu Normal University. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. From May 2000 to July 2003, he was an Assistant Professor in the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he has been an Associate Professor since August 2003. His research interests span many areas including wireless networks, mobile computing, mobile communications, automatic control, and neural networks. He has published over ninety papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Development Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He is listed in Marquis Whos Who in Science and Engineering, Whos Who in America and Whos Who in World.Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for ACM Wireless Networks, an Area Editor for ACM Mobile Computing and Communications Review, an Associate Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications: Wireless Communications Series and the feature editor for Scanning the Literature in IEEE Wireless Communications (formerly IEEE Personal Communications). He has also actively involved with many professional conferences such as ACM MobiCom02, ACM MobiCom01, IEEE INFOCOM04, INFOCOM03, INFOCOM00, INFOCOM98, IEEE WCNC02, WCNC00 (Technical Program Vice-Chair), WCNC99, and International Conference on Computer Communications and Networking (IC3N98) (Technical Program Vice-Chair).Yi-Bing Lin received his BSEE degree from National Cheng Kung University in 1983, and his Ph.D. degree in Computer Science from the University of Washington in 1990. From 1990 to 1995, he was with the Applied Research Area at Bell Communications Research (Bellcore), Morristown, NJ. In 1995, he was appointed as a professor of Department of Computer Science and Information Engineering (CSIE), National Chiao Tung University (NCTU). In 1996, he was appointed as Deputy Director of Microelectronics and Information Systems Research Center, NCTU. During 1997-1999, he was elected as Chairman of CSIE, NCTU. His current research interests include design and analysis of personal communications services network, mobile computing, distributed simulation, and performance modeling. Dr. Lin has published over 150 journal articles and more than 200 conference papers.Dr. Lin is a senior technical editor of IEEE Network, an editor of IEEE Trans. on Wireless Communications, an associate editor of IEEE Trans. on Vehicular Technology, an associate editor of IEEE Communications Survey and Tutorials, an editor of IEEE Personal Communications Magazine, an editor of Computer Networks, an area editor of ACM Mobile Computing and Communication Review, a columnist of ACM Simulation Digest, an editor of International Journal of Communications Systems, an editor of ACM/Baltzer Wireless Networks, an editor of Computer Simulation Modeling and Analysis, an editor of Journal of Information Science and Engineering, Program Chair for the 8th Workshop on Distributed and Parallel Simulation, General Chair for the 9th Workshop on Distributed and Parallel Simulation. Program Chair for the 2nd International Mobile Computing Conference, Guest Editor for the ACM/Baltzer MONET special issue on Personal Communications, a Guest Editor for IEEE Transactions on Computers special issue on Mobile Computing, a Guest Editor for IEEE Transactions on Computers special issue on Wireless Internet, and a Guest Editor for IEEE Communications Magazine special issue on Active, Programmable, and Mobile Code Networking. Lin is the author of the book Wireless and Mobile Network Architecture (co-author with Imrich Chlamtac; published by John Wiley & Sons). Lin received 1998, 2000 and 2002 Outstanding Research Awards from National Science Council, ROC, and 1998 Outstanding Youth Electrical Engineer Award from CIEE, ROC. He also received the NCTU Outstanding Teaching Award in 2002. Lin is an Adjunct Research Fellow of Academia Sinica, and is Chair Professor of Providence University. Lin serves as consultant of many telecommunications companies including FarEasTone and Chung Hwa Telecom. Lin is an IEEE Fellow.     

Joseph L. Locicero September 18, 1947 - July 19, 2008

Joseph L. LoCicero was born on September 18, 1947 in the Borough of The Bronx, New York City, New York, USA. He received his academic training at the City College of New York (BSEE 1970 and MSEE 1971) and the City University of New York (Ph.D. 1977). He performed his doctoral thesis research under Donald L. Schilling. Upon receipt of his doctoral degree he joined Illinois Institute of Technology (IIT) as a faculty member in what is now the Electrical and Computer Engineering (ECE) Department, where he served for over 30 years as Assistant Professor, Associate Professor, Professor, and Motorola Chair Professor, as well as undertaking the position of Acting Chair of the ECE Department for two years. He was one of the co-founders of the Wireless Network and Communications (WiNCom) Research Center.     

Voltage-Mode Universal Biquadratic Filters with One Input and Five Outputs

Four new voltage-mode universal biquadratic filters each with one input terminal and five output terminals are presented. Each of the first two proposed circuits uses four plus-type second-generation current conveyors, two grounded capacitors and five resistors. The third proposed circuit employs two plus-type second-generation current conveyors, one differential voltage current conveyor, two grounded capacitors and five resistors. The fourth proposed circuit employs two multi-output second-generation current conveyors, two grounded capacitors and five resistors. Each of the proposed circuits can realize all the standard filter functions; highpass, bandpass, lowpass, notch and allpass, simultaneously, without changing the passive elements. The proposed circuits enjoy the features of orthogonal controllable of resonance angular frequencies and quality factors, using only grounded capacitors as well as low active and passive sensitivities. Jiun-Wei Horng was born in Tainan, Taiwan, Republic of China, in 1971. He received the B.S. degree in Electronic Engineering from Chung Yuan Christian University, Chung-Li, in 1993, and the Ph.D. degree from National Taiwan University, Taipei, in 1997. From 1997 to 1999, he served as a Second-Lieutenant in China Army Force. From 1999 to 2000, he joined CHROMA ATE INC. where he worked in the area of video pattern generator technologies. From 2000 to 2005, he joined the Department of Electronic Engineering, Chung Yuan Christian University, Chung-Li, Taiwan as an Assistant Professor. Since 2005, he is an Associate Professor. His teaching and research interests are in the areas of Circuits and Systems, Analog and Digital Electronics, Active Filter Design and Current-Mode Signal Processing. Chun-Li Hou was born in Taipei, Taiwan, Republic of China, in 1951. He received the B.S. degree, M.S. degree, and Ph.D. degree in Electrical Engineering from National Taiwan University, Taipei, in 1974, 1976, and 1991, respectively. From 1977 to 1979, he taught as a lecture in Tamkang College. From 1981 to 1991, he taught as a lecture in the department of Electronic Engineering, Chung-Yuan Christian University, Chung, Taiwan. From 1992 until now, he taught there as an Associate Professor. His teaching and research interests are in the areas of Current-Mode Analog Circuit Analysis and Design, Active Network Synthesis Circuit theory and Applications. Chun-Ming Chang obtained his bachelor and master degrees, both in the field of electrical engineering, from National Cheng Kung University, Tainan, Taiwan, R.O. China, and his Ph.D. degree in the field of electronics and computer science from the University of Southampton, U.K. He had been an associate professor in Chung Yuan Christian University in Taiwan from 1985 to 1991, and has been a full professor in the same University since 1991. His research interest is divided by two relative fields, network synthesis before 1991 and analog circuit design after 1991. He had been a chairman of the electrical engineering department in Chung Yuan Christian University from 1995 to 1999. Recently, he was recommended for inclusion in The Contemporary Who's Who of Professionals 2004 Edition, and nominated by the Governing Board of Editors of the American Biographical Institute for the prestigious title MAN OF THE YEAR-2005, and became an Advisor of the ABI's distinguished RESEARCH BOARD OF ADVISORS due to the invention of Analytical Synthesis Method and OTA-Only-Without-C Circuits in the field of analog circuit design. Wen-Yaw Chung was born in Hsin-Chu, Taiwan, R.O.C., 1957. He received the B.S.E.E. and M.S. degrees from Chung Yuan Christian University, Chung Li, Taiwan, in 1979 and 1981 respectively, and the Ph.D. degree in Electrical and Computer Engineering from Mississippi State University, USA, in 1989. Subsequently, he joined the Advanced Microelectronics Division, Institute for Technology Development in Mississippi, where he was involved in the design of a bipolar optical data receiver. In 1990 he worked as a design manager for the Communication Product Division, United Microelectronics Corporation, Hsin-Chu, where he was involved in the design of analog CMOS data communication integrated circuits. Since 1991 he has been an Associate Professor in the Department of Electronic Engineering at Chung Yuan Christian University. His research interests include mixed-signal VLSI design, biomedical IC applications, sensor and actuator interfacing for deep submicron VLSI electronics.     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

A Broadband Quadrature-Modulator with Integrated Baluns

A broadband direct-conversion quadrature-modulator has been implemented in 0.8 m SiGe with integrated baluns in its RF-signal paths. Measured performance includes IRR-values at better than –40 dBc in 0.75–3.6 GHz with output power levels in excess of –20 dBm. For this performance circuit draws 46 mA from a single 2.5 V supply.Esa Tiiliharju was born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland.From 1996 to July 1997 he was employed as assistant at Helsinki University of Technology. He has been holding a position of a research assistant from 1997, and he is currently working towards the Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology.His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is author or co-author for several international refereed conference and journal publications on analog integrated circuits.Kari A.I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987.From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications.Dr. Halonen was an Associate Editor of the IEEE Transactions on Circuits and Systems–Part I: Fundamental Theory and Applications from 1997 to 1999. He has been a Guest Editor for the IEEE Journal of Solid-State Circuits. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.