LIP多重微区域分解算法扩展数字图像动态范围

CCD/CMOS 图像传感器的饱和电流和背景噪音使得一次曝光很难超过 60-80dB 的动态范围。用 LIP(Logarithmic image processing)模式将图像转换为灰色调函数,再将基于 LIP 模式的非线性多重微区域图像分解算法进行改进,可以适应不同亮度的单幅图像处理,提高了可分辨信息量和图像对比度,同时抑止了噪声。质量评价显示,该算法能将 MOS 等级四的源图像提高到等级一。     

Temperature Dependence of Fixed Pattern Noise in Logarithmic CMOS Image Sensors

This paper presents a model that is then simplified to explain the temperature dependence of fixed pattern noise (FPN) in logarithmic complementary metal–oxide semiconductor (CMOS) image sensors. The simplified model uses the average dark response of pixels, which depends only on temperature, to help predict the FPN in the light response, which depends on temperature and illuminance. To calibrate a logarithmic camera, one requires images that are taken at different temperatures and illuminances, which need not be measured, of a uniform stimulus. To correct the FPN in an arbitrary image, one uses the simplified model parameters, which are estimated once by the calibration, and the average dark response, which is infrequently determined by closing the aperture. Through simulation (using mismatch data from a real CMOS process) and experiment (using a commercial logarithmic camera), an improvement is shown in the residual error per image, after calibration, when the proposed method is compared with a related method in the literature that does not account for temperature dependence.      

Modeling, calibration, and correction of nonlinear illumination-dependent fixed pattern noise in logarithmic CMOS image sensors

At present, most CMOS image sensors use an array of pixels with a linear response. However, pixels with a logarithmic response are also possible and are capable of imaging high dynamic range scenes without saturating. Unfortunately, logarithmic image sensors suffer from fixed pattern noise (FPN). Work reported in the literature generally assumes the FPN is independent of illumination. This paper develops a nonlinear model y=a+bln(c+x)+/spl epsi/ of a pixel for the digital response y to an illuminance x and shows that the FPN arises from a variation of the offset a, gain b, and bias c from pixel to pixel. Equations are derived to estimate these parameters by calibrating images of uniform stimuli, taken with varying illuminances. Experiments with a Fuga 15d image sensor, demonstrating parameter calibration and FPN correction, show that the nonlinear model outperforms previous models that assume either only offset or offset and gain variation.     

Transient Response and Fixed Pattern Noise in Logarithmic CMOS Image Sensors

Logarithmic CMOS image sensors are appealing for their high-contrast and high-speed response but they require postprocessing to achieve high-quality images. Previously published work has explained the fixed pattern noise (FPN) in these image sensors using a steady-state analysis. This paper explains how the transient response of the readout circuit may also contribute to FPN. Thus, the performance of these CMOS cameras may be optimized with a proper understanding of the transient response, which is explained here through modeling and simulation with some experimental validation. In particular, the gain variation of a logarithmic camera is shown to be caused primarily by premature digitization. As logarithmic and linear active pixel sensors use similar circuits, some results in this paper, e.g., an analysis of readout capacitance, apply equally to the latter.     

新型光电探测器及其填充系数的确定

详细分析了用于CMOS图像传感器的新型半导体光电器件的工作原理和光电特性,建立解析模型确定由其构成的像素单元的填充系数,优化光电响应特性.由于引入PN注入结,新型光电器件沟道电流同时存在电子电流和空穴电流,提高了器件的响应灵敏度,避免了大的寄生电容,提高了信噪比.     

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-/spl mu/m CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4/spl times/9.4 /spl mu/m/sup 2/ and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution.     

Image Processing Vision Systems: Standard Image Sensors Versus Retinas

To decrease the computational complexity of computer vision algorithms, one of the solutions is to achieve some low-level image processing on the sensor focal plan. It becomes a smart sensor device called a retina. This concept makes the vision systems more compact. It increases performances thanks to the reduction of data flow exchanges with external circuits. This paper presents a comparison relating two different vision system architectures. The first one implements a logarithmic complimentary metal-oxide-semiconductor (CMOS)/active pixel sensor interfaced to a microprocessor, where all computations are carried out. The second involves a CMOS sensor including analog processors allowing on-chip image processing. An external microprocessor is used to control the on-chip data flow and integrated operators. We have designed two vision systems as proof-of-concept. The comparison is related to image processing computation time, processing reliability, programmability, precision, bandwidth, and subsequent stages of computations.     

A Wide-Dynamic-Range CMOS Image Sensor Based on Multiple Short Exposure-Time Readout With Multiple-Resolution Column-Parallel ADC

A wide-dynamic-range CMOS image sensor based on synthesis of one long and multiple short exposure-time signals is proposed. A high-speed, high-resolution column-parallel integration type analog-to-digital converter (ADC) with a nonlinear slope is crucial for this purpose. A prototype wide-dynamic-range CMOS image sensor that captures one long and three short exposure-time signals has been developed using 0.25-mum 1-poly 4-metal CMOS image sensor technology. The dynamic range of the prototype sensor is expanded by a factor of 121.5, compared with the case of a single long exposure time. The maximum DNL of the ADC is 0.3 least significant bits (LSB) for the single-resolution mode and 0.7 LSB for the multiresolution mode     

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

In this paper, a pixel structure called the optimal pseudoactive pixel sensor (OPAPS) is proposed and analyzed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling circuits are also used to suppress fixed-pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352/spl times/288 (CIF) has been designed and fabricated by using 0.25-/spl mu/m single-poly-five-level-metal (1P5M) N-well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 /spl mu/m/sup -2/. The fabricated OPAPS CMOS imager has a pixel size of 8.2/spl times/.2 /spl mu/m, fill factor of 42%, and chip size of 3630/spl times/3390 /spl mu/m. Moreover, the measured maximum frame rate is 30 frames/s and the dark current is 82 pA/cm/sup 2/. Additionally, the measured optical dynamic range is 65 dB. It is found that the proposed OPAPS structure has lower dark current and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus, the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.     

Design, optimization, and performance analysis of new photodiode structures for CMOS active-pixel-sensor (APS) imager applications

The dark current in the active-pixel-sensor (APS) cell of a CMOS imager is known to be mainly generated in the regions of bird's beak after the local oxidation of silicon process as well as the surface damage caused by the implantation of high doping concentration. Furthermore, shallow and deep pn-junctions can improve the photo-sensitivity for light of short and long wavelengths, respectively. In this paper, two new photodiode structures using p-substrate and lightly-doped sensor implant SN- as pn-junction photodiode with the regions of bird's beak embraced by SN- and p-field implants, respectively, are proposed and analyzed to reduce dark current and enhance the overall spectral response. 5 /spl mu/m/spl times/5 /spl mu/m APS cells fabricated in a 0.35-/spl mu/m single-poly-triple-metal (1P3M) 3.3-V CMOS process are designed by using the proposed photodiode structures. As shown from the experimental results, the two proposed photodiode structures of 5 /spl mu/m/spl times/5 /spl mu/m APS cells have lower dark currents of 30.6 mV/s and 35.2 mV/s at the reverse-biased voltage of 2 V and higher spectral response, as compared to the conventional structure and other photodiode structures. Thus, the two proposed new photodiode structures can be applied to CMOS imager systems with small pixel size, high resolution, and high quality.     

Geometric centre tracking of tagged objects using a low power demodulation smart vision sensor

In this study, a modulated light detecting smart CMOS image sensor is presented. The design has the ability to sense asynchronous signals transmitted from electronic markers such as flashing light emitting diodes (LEDs) tagged on moving objects. The geometric centre of the detected region is returned as the output result. With the presented sensor, object localisation and position detection functions are simplified, performed at higher speeds in real time and power requirement is reduced. The sensor in-pixel processing filters out the background image data, detects the modulated marker regions and projects the extracted region on the two axes, while the geometric centre extraction units placed at each axis identify the coordinates assigned to the marker. The design presents less sensitivity to object texture compared with techniques based on edge extraction or binarisation. The sensor has been designed as a 64 x 64 pixel VLSI CMOS chip in the 0.35 μm standard CMOS technology and analysed in the presence of mismatches and noise. Issues such as sensor array scalability, speed and power dissipation are also examined in this study and features of the sensor are reported and compared with some previous designs.     

一种基于数字图像合成的扩展动态范围方法

数码相机中CCD/CMOS图像传感器的饱和电流和背景噪音使得一次曝光很难超过60-80dB 的动态范围。根据人眼对灰度图像的识别特性,可以采用对相同景物二次不同曝光图像软件合成的算法来获取高动态范围的图像。实验结果显示,当景物画面各部分光照明显差别时,这种方法能有效地获得全部细节信息。     

Dark Current and Signal-to-Noise Ratio in BDJ Image Sensors

In this paper, analytical expressions of dark currents and equivalent noise generators of a CMOS color image sensor are presented, and the signal-to-noise ratio (SNR) at both outputs is evaluated. Static measurements and simulations on Austria Micro Systems 0.35-mum CMOS test structures yield guidelines to increase the SNR of the buried double junction photodetector     

Robust Intermediate Read-Out for Deep Submicron Technology CMOS Image Sensors

In this paper, a CMOS image sensor featuring a novel spiking pixel design and a robust digital intermediate read-out is proposed for deep submicron CMOS technologies. The proposed read-out scheme exhibits a relative insensitivity to the ongoing aggressive scaling of the supply voltage. It is based on a novel compact spiking pixel circuit, which combines digitizing and memory functions. Illumination is encoded into a Gray code using a very simple yet robust Gray 8-bit counter memory. Circuit simulations and experiments demonstrate the successful operation of a 64 64 image sensor, implemented in a 0.35 CMOS technology. A scalability analysis is presented. It suggests that deep sub-0.18 will enable the full potential of the proposed Gray encoding spiking pixel. Potential applications include multiresolution imaging and motion detection.     

A CMOS focal-plane motion sensor with BJT-based retinal smoothing network and modified correlation-based algorithm

This work presents and implements a CMOS real-time focal-plane motion sensor intended to detect the global motion, using the bipolar junction transistor (BJT)-based retinal smoothing network and the modified correlation-based algorithm. In the proposed design, the BJT-based retinal photoreceptor and smoothing network are adopted to acquire images and enhance the contrast of an image while the modified correlation-based algorithm is used in signal processing to determine the velocity and direction of the incident image. The deviations of the calculated velocity and direction for different image patterns are greatly reduced by averaging the correlated output over 16 frame-sampling periods. The proposed motion sensor includes a 32/spl times/32 pixel array with a pixel size of 100/spl times/100 /spl mu/m/sup 2/. The fill factor is 11.6% and the total chip area is 4200/spl times/4000 /spl mu/m/sup 2/. The DC power consumption is 120 mW at 5 V in the dark. Experimental results have successfully confirmed that the proposed motion sensor can work with different incident images and detect a velocity between 1 pixel/s and 140,000 pixels/s via controlling the frame-sampling period. The minimum detectable displacement in a frame-sampling period is 5 /spl mu/m. Consequently, the proposed high-performance new motion sensor can be applied to many real-time motion detection systems.     

Evaluation of silicon active pixel sensors for alpha particle detection

Alpha particles can be used as a test stimulus offering several advantages for probing materials of micrometre thicknesses. In this work a silicon CMOS Active Pixel Sensor (APS) is evaluated for alpha particle detection and imaging. These devices can replace traditionally used solid-state track detectors, giving advantages of increased sensitivity, improved linearity and higher dynamic range. CMOS APSs offer high detection efficiency, low noise and digital readout. Qualitative and quantitative analysis of the back-illuminated back-thinned (BT) and standard sensor response to 5.5 MeV alpha particles is presented. Alpha particle detection efficiency was estimated and energy resolution was measured. Imaging capabilities were assessed and quantified. Cluster centroiding algorithms were implemented for image quality improvement.     

Nonlinear coherent optical image processing using logarithmic transmittance of bacteriorhodopsin films

The transmission properties of some bacteriorhodopsin-film spatial light modulators are uniquely suited to allow nonlinear optical image-processing operations to be applied to images with multiplicative noise characteristics. A logarithmic amplitude-transmission characteristic of the film permits the conversion of multiplicative noise to additive noise, which may then be linearly filtered out in the Fourier plane of the transformed image. I present experimental results demonstrating the principle and the capability for several different image and noise situations, including deterministic noise and speckle. The bacteriorhodopsin film studied here displays the logarithmic transmission response for write intensities spanning a dynamic range greater than 2 orders of magnitude.     

CMOS图像传感器的消噪技术

目的　介绍 CMOS图像传感器的消噪技术 .方法　比较了 CMOS图像传感器与CCD图像传感器的优缺点 ,分析了 CMOS图像传感器消噪技术的方法 ,介绍了其研制现状及发展趋势 .结果　目前采用的消噪技术有效地降低了噪声 ,提高了信噪比 .结论　预见了CMOS图像传感器消噪技术的发展趋势 .     

A low-photocurrent CMOS retinal focal-plane sensor with a pseudo-BJT smoothing network and an adaptive current Schmitt trigger for scanner applications

In this work, a new structure of low-photocurrent CMOS retinal focal-plane sensor with pseudo-BJT smoothing network and adaptive current Schmitt trigger is proposed. The proposed structure is very simple and compact. This new circuit can easily be implemented in CMOS technology with a small chip area. Another innovation of this circuit is that the proposed circuit could be operated for low-induced current levels (pA), and the current hysteresis of the proposed current Schmitt trigger could be adjusted adaptively according to the value of induced photocurrents. In this work, the detection of static and moving objects, such as a moving white bar, are proven by projecting a pattern through HSPICE simulation. The proposed retinal focal-plane sensor includes a 32 /spl times/ 32 pixel array with a pixel size of 70 /spl times/ 70 /spl mu/m/sup 2/. The fill factor is 75% and the total chip area is 3000 /spl times/ 3030 /spl mu/m/sup 2/. It is with fully functional 32 /spl times/ 32 implementations consuming less than 8.8 /spl mu/W per pixel at 3.3 V. Measurement results show that the proposed new retinal focal-plane sensor has successfully been used in character recognition of scanner systems, such as pen scanners, etc.     

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager are proposed for scaled standard CMOS technology. The new cell, including a photo diode formed by n-well and p-type substrate and an one-transistor output buffer, shows enhanced characteristics in output voltage swing and sensitivity compared with conventional APS. The imager can achieve fill-factor of 55%, sensitivity of 3.4 V/sec-lux, and large output swing of 2.2 V at V/sub DD/=3.3 V for 0.25-/spl mu/m CMOS technology. In addition, the proposed tunable injection current compensation architecture can improve dynamic range by as much as 40 dB and can be tailor designed to meet various application specifications. A dynamic range of up to 120 dB is projected by simulation results. Experimental results of the new structure, as well as simulated design of the circuit, are presented.