基于gm/Id参数的CMOS运算放大器设计重用方法

模拟电路的设计重用是提高模拟与混合信号集成电路设计效率的重要途径.本文提出了一种基于g_m/I_d参数的不同工艺之间同一结构电路的设计移植方法.方法的基本思想是保持移植前后电路中部分关键MOS管的g_m/I_d参数,从而使移植后电路的性能也基本保持不变.介绍了基于BSIM等模型的g_m/I_d匹配及移植电路参数确定方法.给出了一个Miller补偿两级运放及一个折叠共源共栅运放从0.35μm工艺到0.18μm、0.13μm、90nm工艺的移植仿真结果.与现有方法相比,本文方法可以更小的计算代价,得到性能基本相同、但功耗与面积缩减的电路.     

Analog VLSI Design Constraints of Programmable Cellular Neural Networks

Analog parallel signal processing systems, like cellular neural networks (CNN's), intrinsically have a high potential for perception-like signal processing tasks. The robust design of analog VLSI requires a good understanding of the capabilities as well as the limitations of analog signal processing. Implementation-oriented theoretical methods are described to compute the effect of all types circuit non-idealities with random or systematic causes on the static and dynamical behavior of CNN's and to derive specifications for the cell circuit building blocks. The fundamental impact of transistor mismatch on the trade-off between the speed, accuracy and power performance of CNN chips is demonstrated. A design methodology taking into account the effect of transistor mismatch is proposed and experimental results of a CNN chip implementation designed with this method are discussed.     

面向多功能模拟信号处理的开关电流型可重构模拟电路研究

现有的离散时间型可重构模拟电路采用开关电容技术,存在功能有限、带宽低、与数字CMOS工艺不兼容等问题.本文提出了一种基于电流模取样数据技术的可重构模拟电路,能够与数字CMOS工艺技术兼容.设计了细粒度开关电流型可重构模拟单元,设计了面向开关电流型CAB互连的可编程网络结构.在4×2规模的可重构模拟阵列上,重构实现了三个...     

An Analog Circuit Fault Characterization Methodology

A methodology for diagnosing and characterizing multiple faults in analog circuits, and results from applying this methodology to a real circuit is presented. Our method is a novel combination of a Simulation Before Test (SBT) and Interpolation After Test (IAT) methodology. Our method uses the classical SBT concept of a fault dictionary database constructed before test. It also uses a method of IAT that consists in using the measurements to guide an interpolation algorithm to effectively increase the local resolution of the fault dictionary database and thereby yield the most likely test parameter value. Our methods underlying principle is to characterize the fault-free and faulty circuit cases by their impulse responses obtained by simulation and subsequently stored in a fault dictionary database. The method uses the technique of Lagrange interpolation to resolve the faults between the fault dictionary database entries and the actual measurements. Our experimental results reveal that the method is effective for characterizing faults when the simulations match the measurements sufficiently. Consequently, the methods effectiveness depends highly on the quality of the models used to build the dictionary as well as on the accuracy of the measurements.Yvan Maidon was born in Bordeaux, France. He received the M.Sc degree in (electronics) applied physics from the University of Bordeaux, in 1980. He is currently Head of the Department for Applied Sciences in Electrical and Electronic Engineering at the University of Bordeaux 1. His special research interests include failure analysis and relaibility of analog circuits. He has also developed original BICS for mixed circuits and SoC testing.Thomas Zimmer is currently Professor at the University of Bordeaux 1. He received the M.Sc. degree in physics from the University of Würzburg, Germany, in 1989 and the Ph.D. degree in electronics from the University of Bordeaux 1, France, in 1992. His research interests include characterization and modeling of high frequency bipolar devices. He has authored and co-authored about 70 scientific and technical publications including several book chapters. He is also co-founder of the start-up company XMOD.André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS 02) and the General Chair for VTS 03 and VTS 04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwers Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Societys Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia.     

A Strategy for Rapid Mismatch Evaluation of Transient Characteristics of CMOS Analog Cells

A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.     

PAD: A New Interactive Knowledge-Based Analog Design Approach

This paper presents a new Procedural Analog Design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimize design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface enables instantaneous visualization of design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). The present version of PAD covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers (OTAs) and different operational amplifier topologies. The basic analog structures calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way [1, 2]. Furthermore, PAD provides a layout generator for matched substructures such as current mirrors, cascode stages and differential pairs.Danica Stefanovic was born in 1976. She received the B.S. and M.S. degrees in electrical engineering from the University of Nis (Serbia and Montenegro) in 2000 and 2003 respectively. In 2001/2002 she was a scholarship holder of Swiss Confederation working with Electronic Laboratories, Swiss Federal Institute of Technology (EPFL), on a research project in the domain of analog circuits design techniques and their translation into specific CAD tool. She is currently working towards Ph.D. degree at the Swiss Federal Institute of Technology (EPFL). Her research interests include low power, low voltage analog design methodologies and optimisation techniques.Maher Kayal was born in 1959. He received the M.S. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (EPFL, Switzerland) in 1983 and 1989 respectively.In 1990, he had a Research Associate in the Swiss Federal Institute of Technology. From 1999 he became a professor in the Electronics Laboratories of this institute. He has published many scientific papers and contributed in three books dedicated to mixed-mode CMOS design. His current research interests include: mixed-mode circuit design, sensors, signal processing and CAD tools for analog design and layout automation. He received in 1990 the Swiss Ascom award for the best work in telecommunication fields and in 1997 the best ASIC award at the European Design and Test Conference ED&TC.Marc Pastre was born in 1977. He received the M.S. degree in computer science at EPFL (Swiss Federal Institute of Technology) in 2000. He is currently working towards his Ph.D. at the Electronics Laboratories LEG (EPFL). His research interests include mixed circuits, ADCs/DACs, sensor frontends and CAD tools.     

模拟电路模块级软故障特征的提取与故障诊断

介绍了一种模拟电路故障诊断中功能模块级的单模块软故障模型的建立理论和特征提取的方法,运用该方法提取的单模块故障特征不仅可以有效区分单模块电路中的各类故障,而且单模块电路的故障特征还可以在多模块电路的单故障和多故障的情况下应用。仿真结果表明,通过采样电路输出并进行相应的信号处理来提取故障模型,可以准确地定位多模块故障电路的故障部位。     

SOC设计中的硬核复用及其工艺移植

IP复用已成为SOC(system-on-chip)芯片设计的主要手段之一.以一款0.18 μm工艺下的温度控制芯片设计为例,具体介绍硬核复用设计的工艺移植问题,并给出了一种基于工艺设计工具包的设计流程及其关键技术解决方案.该设计流程在保证电路功能正确性的同时,又可以减少版图设计的设计周期,可以为其他类似硬核的复用设计提供参考.     

工程硕士“模拟集成电路设计”课程探索

本文分析了集成电路专业工程硕士与普通硕士的异同.笔者针对工程硕士培养的教育目标和方向,结合近几年来的教学探索与实践,就工程硕士“模拟集成电路设计”课程在教学内容、教学方法和实验手段等方面进行了探讨,以适应培养复合型和实用性人才的需求.     

微课在“电路与模电”实验课教学中应用研究

为更好的提高实验教学效果,将微课引入“电路与模拟电子技术”实验教学,将实验仪器操作、实验涉及理论、仿真实验、拓展实验等多方面实验内容录制成微课,辅助学生学习、完成实验,解决传统实验教学课时少,内容多、实验模式固定、实验结果单一等问题,帮助提高学生实践应用能力。     

非线性容差模拟电阻电路故障诊断神经网络方法

将线性电路故障定位 l1 范数最优化算法推广到非线性电路的故障定位 ,由于测后计算是基于神经网络计算机环境 ,所需时间较少 ,能满足现代工业实时性需要。实例和计算机模拟结果表明所提方法是可行的     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

模拟电路教学改革研讨

文章从教学内容改革、教学方法设计、考试改革三个方面,阐述了模拟电路教学的改革方法,探索了提高教学质量及学生能力培养的新途径.文章认为教师自身应加强专业技能的学习训练,在教学过程中应强化学生的主体作用,激发学生学习的积极性,加强学生自学能力的培养,注重现代化教学手段的应用,进而实现提高教学质量的目的.     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

模拟电子技术教学方法的多样化

“模拟电子技术”课程是一门重要的基础课程,围绕该课程的教学改革和探讨一直在进行中。本文在教学方法上作了一些有益的尝试,就板书与多媒体相结合的授课方法、学生入门的难点、设计性课题的必要性、学生兴趣的培养和教学过程中教师的视角等问题进行了较为深入的分析和探讨。教学实践表明,通过这些教学方法的尝试,可以提高学生对课程的兴趣,增强学生对知识的理解程度,收到了更好的教学效果。     

模拟电路故障分析与诊断方法研究

随着电子技术的飞速发展,集成电路的应用覆盖了社会的方方面面,但集成电路模拟部分故障难于分析与诊断的问题在很大程度上限制了它的开发维修成本与实际工作效应。该文分析了经典与现代的模拟电路故障分析方法,比较了他们的优点与不足,并结合实际状况提出新的故障分析与诊断方法的研究思路。     

一种低压BiCMOS四象限模拟乘法器的设计

提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。