High-efficiency 35-GHz GaAs MESFET's

Ka-band GaAs FET's with power output in excess of 200 mW and with efficiencies of more than 20 percent are described. Both ion-implanted and VPE-grown wafers were used. Deep UV (300-nm) lithography and chemical etching was employed to obtain a final gate length of 0.5 µm. These FET chips were flip-chip mounted and had a very low thermal resistance of 50°C/W for a total source periphery of 0.6 mm. At 35 GHz an output power of 220 mW with 21-percent efficiency at 3-dB gain was obtained from a 0.6-mm cell.     

InP depletion-mode microwave MISFET's

Depletion-mode aligned-gate InP MISFET's with gate lengths of 1.5-1 µm have given output power of 1.26-W/mm gate width and power-added efficiencies of up to 40 percent at 4 GHz. At 12 GHz, 0.75-W/mm gate width with 22-percent power-added efficiency was obtained. At 18 GHz, a power output of 331 mW (0.59 W/mm) with 3.1 dB of gain and 15.7-percent power-added efficiency was measured. An output power of 245 mW (0.44 W/mm) with 3-dB gain and 10.7-percent efficiency was obtained at 20 GHz.     

Light intensity profiles of surface-emitting InGaAsP LED's: Impact on coupling to optical fibers

Light intensity profiles of 1.3-µm surface-emitting InGa AsP/InP LED's were measured using an infrared vidicon imaging technique. Typical light spot profiles were shown to have uniform intensity only over a small spot, with significant Gaussian tails around the periphery. Profiles were measured versus current. Narrowing of the light spot via current crowding was observed. A previous model for current crowding in stripe-geometry lasers was modified to calculate intensity profiles of circular-contact LED's. The model qualitatively predicts the observed changes in the profile shape with varying current and epitaxial-layer parameters. Measured efficiencies η of coupling LED power to optical fibers are usually lower than calculated for an ideal Lambertian source of uniform intensity. The observed profile is shown here to be responsible for the reduced η. For example, η of a uniform 25-µm spot is calculated to be ∼30-percent higher than that of a spot with typical Gaussian spreading and a width of 25 µm at half-maximum intensity, both butt-coupled to a 50-µm core, graded-index fiber. Lensing schemes to improve η were designed assuming uniform light spots, A ray-tracing calculation shows here that spherical lenses improve η equally well in the presence of Gaussian tails around the light spot.     

Improving resolution in photolithography with a phase-shifting mask

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10X tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.     

High-efficiency millimeter-wave GaAs/GaAlAs power HEMT's

The power, gain, and efficiency of 0.5-µm gate-length, 75- and 50-µm gate-width multiple heterojunction high electron mobility transistors (HEMT's) have been evaluated from 10 to 60 GHz. At 10 GHz, with a source-to-drain voltage as low as 2.4 V, the device delivers a power density of 0.37 W/mm with 13.4-dB gain and 60.8-percent efficiency. At 60 GHz, a 50-µm device gave 0.4 W/mm with 3.6-dB gain and 14-percent efficiency. The power density and efficiency of these 0.5- µm gate-length HEMT's above 40 GHz are the best reported for a three-terminal device. Fundamental frequency oscillations up to 104 GHz were observed when a device was bonded as a free-running oscillator.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

Steep profile resist patterns through 1:1 deep UV projection printing

Steep profile resist patterns of 1 µm lines and 1 µm spaces are delineated by 1:1 projection printing using a novel, deep uv, negative resist. Strong absorption of deep uv light and the absence of swelling caused by the developer contribute to the high resolution of the resist. The sensitivity is adequate and the optimum scanning exposure time for a 4 inch wafer is about one minute. The processing procedure is the same as that for conventional photolithography.     

Al/Si contact resistance for submicrometer design rules

The resistance of contacts between aluminum/1.5-percent silicon and doped silicon is experimentally determined as a function of contact sizes from 0.6 to 4 µm square. Silicon contacted was doped to varied concentrations with either boron or phosphorus. The magnitudes of resistances observed for submicrometer geometry contacts underscore the need for a lower resistance-contact process for high-performance VLSI.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

A Room‐Temperature High‐Conductivity Metal Printing Paradigm with Visible‐Light Projection Lithography

Fabricating electronic devices require integrating metallic conductors and polymeric insulators in complex structures. Current metal‐patterning methods such as evaporation and laser sintering require vacuum, multistep processes, and high temperature during sintering or postannealing to achieve desirable electrical conductivity, which damages low‐temperature polymer substrates. Here reports a facile ecofriendly room‐temperature metal printing paradigm using visible‐light projection lithography. With a particle‐free reactive silver ink, photoinduced redox reaction occurs to form metallic silver within designed illuminated regions through a digital mask on substrate with insignificant temperature change (<4 °C). The patterns exhibit remarkably high conductivity achievable at room temperature (2.4 × 10⁷ S m^?1, ≈40% of bulk silver conductivity) after simple room‐temperature chemical annealing for 1–2 s. The finest silver trace produced reaches 15 µm. Neither extra thermal energy input nor physical mask is required for the entire fabrication process. Metal patterns were printed on various substrates, including polyethylene terephthalate, polydimethylsiloxane, polyimide, Scotch tape, print paper, Si wafer, glass coverslip, and polystyrene. By changing inks, this paradigm can be extended to print various metals and metal–polymer hybrid structures. This method greatly simplifies the metal‐patterning process and expands printability and substrate materials, showing huge potential in fabricating microelectronics with one system.     

A new Ga0.47In0.53As field-effect transistor with a lattice-mismatched GaAs gate for high-speed circuits

A novel thin GaAs lattice-mismatched gate Ga0.47In0.53As field-effect transistor (LMG-FET) is reported. The device shows an extrinsic dc transconductance of 108 mS/mm for a 1.4-µm gate length and 240-µm gate width. Despite a 3.7-percent, lattice mismatch between GaAs and Ga0.47In0.53As, the LMG-FET shows stable operation even at 80°C (with a 13-percent increase in transconductances), exhibits negligible current drift, and suffers very little change in threshold voltages (<0.05 V) under illumination, This technology may find applications in high-speed lightwave transmission as well as high-speed digital circuits.     

A study of projected optical images for typical IC mask patterns illuminated by partially coherent light

Optical projection printing using partially coherent illumination is simulated for one micrometer and half micrometer objects representative of typical mask patterns such as contact holes, rectangular bars and openings, intersections of perpendicular lines, and adjacent lines of unequal lengths. The image intensity distributions in absorptionless photoresists on nonreflective substrates are plotted as sets of constant intensity contours. For each pattern and illumination, an exposure-defocus (E-D) diagram is generated by evaluating the combined exposure and defocus tolerance yielding linewidths within ±2.5 percent of the mask linewidth. Besides comparing the image and ED margins of different object shapes and sizes, the effects of high versus low degrees of coherence, single versus dual wavelength, as well as long-wavelength high NA versus short-wavelength low NA were studied using the 1-µm rectangular opening.     

The use of submicrometer electron-beam lithography for fabricating 4-kbit CCD memory arrays

A 4-kbit CCD memory array has been fabricated using electron-beam lithography for the high-resolution patterns and projection lithography to define the low-resolution features. The basic CCD cell size is 3.2 µm × 4.2 µm consisting of a storage area 2.4 µm × 3.6 µm with a 0.8-µm barrier and a 0.6-µm channel stop. To make these small CCD's, as well as the associated short-channel MOSFET's, we modified the conventional MOS wafer processing. The new process for two-level polysilicon gates requires six electron-beam levels with a minimum resist feature of 0.3 µm. Alignment of the electron-beam patterns uses Ta benchmarks which we found to be compatible with MOS devices. Testing of the 4-kbit array and other shift resisters showed submicrometer channel-stops and barriers are feasible while maintaining low channel-to-channel crosstalk and charge-transfer efficiency greater than 0.9995. In addition, low capacitance output circuits defined by electron-beam lithography can detect the small number of charges in the high-resolution CCD's and amplify the signal sufficiently to recirculate the data.     

X-band self-aligned gate enhancement-mode InP MISFET's

Self-aligned gate enhancement-mode InP/SiO2MISFET's with ∼0.8-µm channel length were successfully fabricated on an Fe-doped semi-insulating substrate. The fabricated MISFET's exhibited very high transconductance, as high as 200 mS/mm, and goodX-band operation, especially marked high-power-output characteristics. The minimum noise figure at 4 GHz was 1.87 dB with 10.0-dB associated gain. 1.17 W/mm and 1.0 W/mm power outputs were obtained at 6.5 and 11.5 GHz, respectively. 43.5-percent maximum power-added efficiency was attained at 6.5 GHz.     

Fabrication and thermal performance of a novel TRAPATT diode structure

The development of TRAPATT diodes for long-pulse operation (10 to 100 µs), high duty cycle (1 to 15 percent), and wide bandwidth (12 percent), for phase array systems atFband requires new device fabrication and new heat-sinking technology. A novel TRAPATT diode in the form of interconnected long strips having high periphery-to-area ratio (cruciform) has been designed and fabricated. In this paper we described the thermal properties of the cruciform structure diode, which sustains 50-µs pulse width at 5.5-percent duty cycle while delivering 68-W RF power at 5-dB gain and 9-percent added efficiency, in addition to 100-µs pulse width at 4.2-percent duty cycle while delivering 50-W RF power output ast 3.6-dB and 5.5-percent added efficiency, both as narrow-band amplifier.     

A lithium niobate light modulator for fiber optical communications

An electrooptic intensity modulator using lithium niobate has been developed for applications in binary fiber optical digital communications at the wavelength of 1.06 µm. We have shown that many shortcomings generally associated with electro-optic modulators can be surmounted. The modulator was driven by a compact transistor amplifier, temperature dependence of the static birefringence was minimized, and the optical bias was made adjustable by a dc voltage superposed on the signal. The modulator has been operated at 70-Mb/s pulse rate and 100-percent modulation, its extinction ratio is better than 40 to 1 and the optical insertion loss is about 1 dB.     

An AC-powered experimental memory circuit with a resistively loaded sense circuit

The design and fabrication of an ac-powered experimental memory circuit for Josephson cache memories are reported. The circuit contains a memory cell array and a sense circuit. The sense circuit consists of RCJL gates, symmetrical three-junction sense gates, and transmission lines. An experimental memory circuit has been fabricated by 2-µm Pb-alloy processes. A proper circuit operation, has been verified using a bipolar trapezoidal waveform current. A ±23-percent sense current margin and a ±29-percent OR gate bias current margin were obtained. A typical 130-ps sense time was estimated for a 1-kbit memory by computer simulations.     

Tapered windows in phosphorus-doped SiO2by ion implantation

Phosphorus-doped SiO2is frequently used as a dielectric coating in silicon integrated circuits. It is important that windows in this dielectric have sufficiently tapered walls so that the subsequent metallization has good step coverage. It is shown here that tapered windows can be made in both Nitrox-deposited ∼ 1-percent phosphorus-doped SiO2and Silox-deposited ∼ 7-percent phosphorus-doped SiO2as well as undoped SiO2by an ion implantation which produces a thin damaged layer at the top of the oxide. The damaged layer etches at a faster rate than the undamaged oxide. This fast-etching layer undercuts the photoresist which serves as the etching mask and results in window walls having slopes in the range of 30-40° with respect to the wafer surface. Tapering windows by ion implantation is a dependable process that gives reproducible results without having to rely on the art of photoresist liftoff methods.     

An electron beam maskmaker

An electron beam machine is described, in which the ¼-µm diameter beam is computer controlled to define integrated circuit and other fine patterns at their final size in response to a coordinate data input. Electron sensitive resist is exposed on metallized quartz or glass substrates. Resist development followed by metal etching enables masks to be made, either for subsequent photolithography or, more usually, for use in the electron image projector developed by J. P. Scott. The mask drawing process is entirely automatic and the emphasis is on the rapid generation of complex patterns with high precision. A two-stage deflection system enables rectangular pattern elements to be drawn at a 10-MHz stepping rate and accurately positioned throughout a 2-mm square main deflection field. Patterns are automatically positioned, to an accuracy of ±1/8 µm, relative to an array of markers predeposited on the substrate. The beam is also refocused automatically at the markers. A mechanical stage for the substrate enables 50 × 50-mm arrays of patterns to be built up. A complete mask containing detail as small as 1 µm takes 1-3 h to draw. Finer patterns can be drawn, although more slowly.     

An EBS (electron bombarded semiconductor) high-current pulse amplifier

An EBS (electron bombarded semiconductor) pulse amplifier which generates high-current fast-risetime variable-width pulses into low impedance loads is described. Current pulses of 100 A into a 1-Ω load have been obtained with a risetime of 2.2 ns. A di/dt of 40 000 A/µs and a dV/dt of 71 000 V/µs have been obtained. Pulse lengths to 1 µs at 0.1-percent duty have been achieved. The risetime and peak current capabilities are presently limited by internal circuit parasitics. Without parasistics, the theoretical peak output capabilities for this EBS are 340 A with a di/dt of 6 × 10⁵A/µs.