A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

一种快速响应LDO环路设计

设计一种带快速响环路的低压差线性稳压器(LDO)。该系统通过电容对高频或快速变化的输出电压反馈回路进行短路,提供一条对输出电压变化的快速响应通路。输出缓冲级为后极调整管提供大的电流输出并提高系统栅极节点的极点频率。该系统具有响应速度快、稳定性高的特点,可广泛应用于不同的低压差线性稳定器。     

An adaptive resonant filter

A solid-state adaptive (analog storage) device with stable electrical characteristics is described and demonstrated. The device is a resonant bandpass electronic filter with adaptable voltage gain; that is, the voltage gain-frequency transfer characteristic can be "set" to different values of attenuation by the application of an adapt signal and will retain that "setting" after the adapt signal has been removed. Ferroelectric materials are used as the dielectric in a filter structure composed of two capacitors bonded together so that resonant mechanical vibrations established in one (the input resonator) are coupled to the other (the output resonator). Converse and direct piezoelectric effects generate the mechanical vibrations and the output voltages, respectively. Ferroelectric effects in either capacitor provide the analog storage capabilities. The acoustical coupling mechanism employed in the device design results in electrically stable device characteristics. Previous ferroelectric adaptive devices used unstable field effect coupling mechanisms which led to unacceptable device performance. Experimental adaptive resonant filters fabricated with ceramic lead zirconate-lead titanate material compositions are discussed. These filters have electronic Q values near 100 at resonant frequencies in the range 10²to 10⁷Hz. The voltage gain-frequency characteristic has a maximum value at resonance of about 0 to +10 dB. Application of a voltage adapt pulse (100 to 300 volts) of low energy (mJ) to either side of the filter can adapt the entire gain characteristic by any value between 0 and about -60 dB within an arbitrary switching time (limited to a practical range of roughly 10⁺³to 10^-4seconds) as determined by the pulse amplitude. Voltage gain settings are electrically stable and can be reproduced by the same or an equivalent sequence of adapting pulses.     

A source-follower type analog buffer using poly-Si TFTs with large design windows

New simple source follower circuits using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) as analog buffers for the integrated data driver circuit of active-matrix liquid crystal displays and active-matrix light emitting diodes are discussed. In addition to the threshold voltage difference of driving TFTs, the unsaturated of output voltage arisen from the significant subthreshold current will also result in the difficulty of the buffer circuit design. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics.     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

带修调的高稳定LDO线性稳压器

提出了一种新型高稳定LDO电路。该电路采用折叠型共源共栅运算放大器作为误差放大器,通过消除零点的密勒补偿技术提高环路稳定性;并在反馈电路中加入一种新的电压调整模块,以保证输入参考电压在一定范围内发生偏离时都能得到相同的输出电压。基于0.8μm 40VBCD工艺,对提出的LDO电路进行了HSPICE仿真验证。结果表明,在输入参考电压发生±17%的变化时,输出电压仅变化±3.8%。     

一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对(极零对的产生没有增加静态功耗),不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作.由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要;而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度.该LDO基于0.5μm CMOS工艺实现.后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压(dropout电压)仅为120mV.     

一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.     

A programmable multi-output technique in LDO regulator for multi-reference SAR ADC application

A multi-output and high-precision output-tuning technique in a low-dropout regulator (LDO) for multi-reference low-power SAR ADC is proposed in this article. A programmable resistor string is utilised for multi-output, and a tuneable resistor ladder is introduced in the feedback network for high-precision LDO output control. The applicability and superiority of this proposed approach are verified by the design of a 65 nm CMOS LDO with programmable output. The design results show that the LDO output ranges from 0.4 to 1.2 V with 0.2 V/step, and the output voltage can be precisely tuned by 0.05 V/step within a range of 0.8–1.15 V. The line regulation of this LDO is about 0.27 mV/V. The multi-output ability enables the LDO to drive five light loads simultaneously, and the high-precision tuning ability can effectively overcome the output errors caused by power supply variation, temperature drift and other non-ideal factors.     

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.     

用于低压差线性稳压器的输出精密微调设计技术

提出了一种用于低压差线性稳压器(LDO:Low-Dropout regulator)的输出精密微调方法,通过在反馈网络中引入可微调电阻梯实现对LDO输出的精密调整,并采取伪电阻保护的版图布局方式提高电阻梯的匹配性能。基于65 nm CMOS工艺对LDO进行了设计,整个LDO线性调整率约为0.05mV/V,输出电压在1.02V~1.36V范围内能够按照0.02V/step的最小步长进行精密微调,能有效减小由电源电压、温度等因素引起的输出误差,适合嵌入式片上系统(So C:System-on-Chip)的应用。     

An adaptive ferroelectric transformer—A solid-state analog memory device

A new solid-state adaptive (analog memory) device is described and demonstrated. The device is a flat-band electronic transformer with adaptable voltage gain; that is, the voltage gain-frequency transfer characteristic can be "set" to different values of attenuation by the application of an adapt signal and will retain that setting after the adapt signal has been removed. Ferroelectric materials are used as the dielectric in the transformer structure composed of two capacitors bonded together so that mechanical vibrations established in one (the input capacitor) are coupled to the other (the output capacitor). Converse and direct piezoelectric effects generate the mechanical vibrations and the output voltages, respectively. Ferroelectric effects in either capacitor provide the analog memory capabilities. Experimental adaptive transformers demonstrated are suitable for audio frequency operation. The voltage and current gain-frequency transfer characteristics are flat over the entire audio frequency range. Maximum gain is typically about -20 dB. Application of a voltage pulse (100 to 300 volts) of low energy (mJ) to either side of the transformer can adapt the gains to specific lower settings (between-20 and -60 dB) within an arbitrary switching time (roughly 10⁺³to 10^-4seconds) as determined by the pulse amplitude. Gain settings are electrically stable to within a few percent of the maximum gain for periods of at least one year, and possibly indefinitely, and can be reproduced by the same or an equivalent sequence of adapting pulses.     

用于GaN HEMT栅驱动芯片的快速响应LDO电路

设计了一种用于GaN高电子迁移率晶体管(High-Electron-Mobility Transistor,HEMT)器件栅驱动芯片的快速响应低压差线性稳压器(Low Dropout Regulator,LDO)电路,可为高速变化的数字电路提供快速响应的供电电压。该电路采用动态偏置结构,通过在大负载发生时给误差放大器增加一个额外的动态偏置结构,来加快输出端的瞬态响应速度。基于0.18μm BCD工艺,完成了电路设计验证。仿真结果显示LDO瞬态响应时间小于0.5μs,可满足频率达1 MHz的GaN HEMT器件栅驱动芯片应用要求。     

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout(LDO)regulator for system-on-chip(SoC)applications is presented.By adopting AC-boosting and active-feedback frequency compensation(ACB-AFFC),the proposed LDO enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high.The LDO regulator is designed and fabricated in a 0.6/am CMOS process.The active silicon area is only 770×472μm2.Experimental results show that the total error of the output voltage due to line variation is less than ±0.1 97%.The load regulation is only 0.35 mV/mA when the load current changes fromoto 100mA.     

一种快速响应低压差线性稳压器的设计

介绍了一种应用于DRAM芯片内部供电的新型低压差线性稳压器(LDO)。在传统LDO电路PMOS输出驱动管的栅端增加了一个开关电容电路,根据负载电流使能信号控制耦合电容的接入,使驱动管的栅端耦合到一个正向或者负向的电压脉冲,在负载电流急剧变化时能快速调整过驱动电压,以适应负载电流的变化。仿真结果显示,该电路有利于输出电压的快速稳定,恢复时间缩短了38%以上。采用45 nm DRAM 掩埋字线工艺进行流片。实测结果显示,该LDO输出电压恢复时间在10 ns以内。在DDR3-1600的数据传输速度下,DRAM芯片的数据输出眼图为280 ps,符合JEDEC标准。     

基于LDO电压调整器的带隙基准电压源设计

设计一款应用于电压调整器（LDO）的带隙基准电压源。电压基准是模拟电路设计必不可缺少的一个单元模块,带隙基准电压源为LDO提供一个精确的参考电压,是LDO系统设计关键模块之一。本文设计的带隙基准电压源采用0.5μm标准的CMOS工艺实现。为了提高电压抑制性,采用了低压共源共栅的电流镜结构,并且在基准内部设计了一个运算放大器,合理的运放设计进一步提高了电源抑制性。基于Cadence的Spectre进行前仿真验证,结果表明该带隙基准电压源具有较低的变化率、较小的温漂系数和较高的电源抑制比,其对抗电源变化和温度变化特性较好。     

一种衬底波纹注入的宽频带高PSR无片外电容LDO

基于40 nm CMOS工艺,设计了一种具有高频高电源抑制(PSR)的无片外电容 低压差线性稳压器(LDO)电路。电路采用1.1 V电源供电,LDO输出电压稳定在0.9 V。仿真结果表明,传统无片外电容LDO电路的PSR将会在环路的单位增益 频率(UGF)处上升到一个尖峰,之后才经输出节点处的电容到地的通路开始降低,最高时PSR甚至大于0 dB。采用新型的衬底波纹注入技术的LDO能很好地抑制PSR的尖峰,可以做到全频段都在-20 dB以上,相比传统结构,尖峰处的PSR提高了20 dB以上。该LDO适用于需要低电压供电的射频电路。     

A dual body SOI structure for mixed analog-digital mode circuits

A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFET's are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body resistance, and the self-heating effect, it is shown that the proposed structure is promising for SOI technology in mixed analog-digital mode circuit applications