Schottky Barrier Characteristics of Cobalt–Nickel Silicide/n-Si Junctions for Scaled-Si CMOS Applications

Ternary cobalt–nickel silicide/n-Si Schottky diodes have been fabricated by sputtering using an equiatomic cobalt–nickel alloy target. A minimum sheet resistivity of the ternary silicide is found to be 5–7 $Omega / hbox{sq}$. Grazing-incidence X-ray diffraction shows the formation of ternary silicide phases. Cross-sectional TEM micrograph shows a fairly uniform diffusion of metals into Si with the formation of fully silicided film. Selected-area electron diffraction pattern exhibits the crystalline nature of the silicide layer. Temperature-dependent electrical current–voltage measurements have been used to characterize an optimized Schottky diode formed by annealing at 450 $^{circ}hbox{C}$. The room-temperature barrier height and ideality factor are found to be 0.656 eV and 1.6, respectively, from the $I$ –$V$ characteristics. The series resistance of the diode has been calculated and is found to be 1–11.8 $hbox{k}Omega$ . The variation of barrier height has been attributed to the inhomogeneity in Schottky junction.      

Schottky Barrier N-Type Thin Film Transistors With Polycrystalline Silicon Channel and Er-Silicided Metallic Junctions

N-type Schottky barrier thin film transistors (SB-TFTs) with polycrystalline silicon channel and metallic junctions were fabricated by using Er silicidation, and electrical structural properties were compared to conventional TFTs with phosphorous-doped source/drain regions. The performances of SB-TFTs are better than that of the conventional TFTs. A forming gas annealing process leads to a great improvement in the characteristics of both devices. In particular, excellent electrical characteristics were obtained from the forming gas annealed SB-TFTs: the subthreshold swing of 180 mV/dec, the drive current of $hbox{1.47} times hbox{10}^{-5} hbox{A}$, and the on/off current ratio of $ hbox{5} times hbox{10}^{6}$.      

微波肖特基势垒二极管硅化物工艺技术研究

对微波肖特基中、低势垒二极管硅化物的工艺技术进行了研究。用Ｎｉ－Ｓｉ硅化物作中势垒硅化物,用Ｔｉ－Ｓｉ硅化物作低势垒硅化物。通过设计和工艺实验,得到温度、时间、真空度等取佳工艺技术条件。在保持微波肖特基二极管势垒特征的同时,提高了反向电压,增强了它的稳定性和可靠性。     

短沟道源极肖特基势垒SOI MOSFET研究

随着MOSFET的特征尺寸的不断减小,短沟道效应越来越严重,阻碍了器件尺寸的进一步按比例缩小。如何有效地抑制短沟道效应已经成为当今的热门研究课题。本文提出了一种新型的SOI MOSFET结构,该结构漏极采用重掺杂的欧姆接触,源极采用肖特基接触。借助于SILVACO TCAD仿真工具,仿真出了该器件的各项性能参数,并与普通的SOI MOSFET进行对比研究,结果显示这种源极肖特基势垒SOI MOSFET能够更有效地抑制短沟道效应,且具有更大的输出电阻、更低的亚阈值电流和功耗。     

用于肖特基势垒红外传感器的Ir及IrSi膜

本文叙述了在 P-Si 基片上,采用物理沉积方法制备高纯 Ir(铱)膜。讨论了在300～1000℃退火温度下,Si-Ir 界面反应形成 IrSi 硅化物的研制技术和工艺参数。分析了界面反应机理、IrSi 膜的光电学特性。最后介绍了 IrSi 在肖特基势垒红外(SBIR)固体传感器研制技术中的应用。     

Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO₂. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm²/Vs have been found for GdSiO.     

Tuning of the Nickel Silicide Schottky Barrier Height on p-Type Silicon by Indium Implantation

In this letter, indium (In) implantation is introduced as a method to tune the Schottky barrier height of nickel silicide (NiSi) contacts formed on p-type silicon. Indium implantation is performed prior to NiSi formation and the implant conditions are chosen such that the implanted region is entirely consumed by the silicide. During silicide formation, some of the indium segregates at the NiSi–Si interface and can have a significant impact on the Schottky barrier height. It is shown that the barrier height decreases almost linearly with the In dose from 0.37 eV on p-type Si to 0.16 eV with an In dose of $hbox{1} times hbox{10}^{14} hbox{cm}^{-2}$ on p-type Si.      

Tuning of the Platinum Silicide Schottky Barrier Height on n-Type Silicon by Sulfur Segregation

The Schottky barrier height $Phi_{B}$ of platinum silicide (PtSi) contacts on n-type silicon was tuned by sulfur segregation at the PtSi/Si interface. Sulfur was implanted prior to Pt deposition and segregated at the interface during PtSi formation. It was observed that the barrier height could be tuned by changing the sulfur dose. A minimum barrier height of 0.12 eV was obtained on n-type (100) Si substrates. Since PtSi naturally provides a small $Phi_{B}$ of 0.2 eV on p-type Si, it carries the potential to serve as the single metal source/drain contact metal in a CMOS integrated circuit with $Phi_{B}$ tuning on n-channel transistors.      

Microwave performance of SOI n-MOSFETs and coplanar waveguides

The microwave performance of 1-μm gate-length n-MOSFETs fabricated on both SIMOX and BESOI substrates was measured. The process included a self-aligned silicide in an otherwise conventional MOS sequence. Initial optimization yielded devices with an f_max of 14 GHz on BESOI and 11 GHz on SIMOX. Coplanar waveguides (CPWs) were fabricated on substrates with resistivities from 4 to 4000 Ω-cm. A loss of 1.8 dB/cm at 2 GHz was demonstrated on the 4000-Ω-cm float-zone substrate     

钨硅化物砷化镓Schottky接触的形成和特性

本文报道了钨硅化物-砷化镓Schottky接触的形成过程和电学特性.实验表明,WSi_x/GaAs Schottky接触具有优越的I-V特性,势垒高度保持在0.8V,理想性因子实际上保持在1,并具有高温稳定性.研究表明,除了硅化物的成份,表面处理工艺和硅化物淀积技术也将对Schottky接触的I-V特性和热稳定性产生强烈的影响.本文提出利用对GaAs衬底的溅射腐蚀和在淀积过程中加以负的衬底偏置能显著地改进金属层与衬底的粘附性.     

Noise Reduction in GaAs Schottky Barrier Mixer Diodes (Short Paper)

The sensitivity of heterodyne receivers operating at millimeter and submillimeter wavelengths is limited by the noise produced in the mixer element. In this paper we investigate the presence of excess noise in GaAs Schottky barrier mixer diodes. Comparison of the measured noise data with that predicted from noise models indicates that these devices typically exhibit excess noise. An additional fabrication step, which removes several hundred angstroms from the GaAs surface before the anode contact is formed, greatly reduces this excess noise. This additional step is outlined, and experimental evidence is presented.     

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses $({T}_{rm SOI})$ on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker ${T}_{rm SOI}$ device, the thinner ${T}_{rm SOI}$ device with high-strain CESL possesses a higher interface trap $({N}_{rm it})$ density, leading to degradation in the device performance. On the other hand, however, the thicker ${T}_{rm SOI}$ device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker ${T}_{rm SOI}$ has a higher bulk oxide trap $({N}_{rm BOT})$ density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker ${T}_{rm SOI}$ devices in this strain technology.      

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

Radiation source dependence of performance degradation in thin gate oxide fully-depleted SOI n-MOSFETs

The degradation of the electrical performance of thin gate oxide fully depleted SOI n-MOSFETs and its dependence on the radiation particles are investigated. The transistors are irradiated with 7.5-MeV protons and 2-MeV electrons at room temperature without bias. The shift of threshold voltage and the coupling effect with the degraded opposite gate are clarified. A remarkable reduction of the floating body effects is observed after irradiation. The degradation of the extracted parameters is discussed by a comparison with the damage coefficients.     

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.     

Measurement and simulation of floating substrate effects on the intrinsic gate capacitance characteristics of SOI n-MOSFETs

The theoretical foundation of unique floating substrate effects, which have been observed experimentally, on the intrinsic gate capacitance characteristics in saturation of SOI N-MOSFETs, is clearly established using original two-dimensional numerical device simulations.<>     

Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation

Degradation of the electrical performance in partially depleted SOI MOSFETs by 2-MeV electrons is presented. The degradation behavior of the 2^nd transconductance (g_mf) peak and its dependence on the back gate voltage is discussed taking into account the degradation of the back gate. The drain current in the subthreshold region is increased by irradiation. This is caused by the turn-on of the parasitic edge transistor. The 2^nd peak in the transconductance (g_mf) tends to decrease after irradiation, while less degradation is observed in the 1^st g_mf peak. The decrease of the 2^nd g_mf peak enhances by the application of a negative V_BG and the result can be explained by the degradation of the Si/buried oxide interface and the increase of the sidewall leakage, which gives rise to a lowering of the body potential.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

Ni/4H-SiC肖特基势垒二极管研制

采用微电子平面工艺,高真空电子束热蒸发金属Ni分别作肖特基接触和欧姆接触,二级场限环终端表面保护,研制出Ni/4H-SiC肖特基势垒二极管(SBD)。I-V特性测量说明,Ni/4H-SiCSBD有较好的整流特性,热电子发射是其主要的运输机理。反向击穿电压达1500V,理想因子为1.2,肖特基势垒高度为0.92eV。