A DC-20-GHz InP HBT balanced analog multiplier for high-data-ratedirect-digital modulation and fiber-optic receiver applications

This paper reports on a dc-20-GHz InP heterojunction bipolar transistor (HBT) active mixer, which obtains the highest gain-bandwidth product (GBP) thus far reported for a direct-coupled analog mixer integrated circuit (IC). The InP HBT active mixer is based on the Gilbert transconductance multiplier cell and integrates RF, local oscillator, and IF amplifiers, High-speed 70-GHz f_T and 160-GHz f_max InP HBT devices along with microwave matching accounts for its record performance. Operated as a down-converter mixer, the monolithic microwave integrated circuit achieves an RF bandwidth (BW) from dc-20 GHz with 15.3-dB gain and benchmarks a factor of two improvement in GBP over state-of-the-art analog mixer ICs. Operated as an up-converter, direct-digital modulation of a 2.4-Gb/s 2³¹ -1 pseudorandom bit sequence (PRBS) onto a 20-GHz carrier frequency resulted in a carrier rejection of a 28 dB, clock suppression of 35 dBc, and less than a 50-ps demodulated eye phase jitter. The analog multiplier was also operated as a variable gain amplifier, which obtained 20-dB gain with a BW from dc-18 GHz, an third-order intercept of 12 dBm, and over 25 dB of dynamic range. A single-ended peak-to-peak output voltage of 600 mV was obtained with a ±35-mV 15 Gb/s 2⁵-1 PRES input demonstrating feasibility for OC-192 fiber-telecommunication data rates. The InP-based analog multiplier IC is an attractive building block for several wideband communications such as those employed in satellites, local multipoint distribution systems, high-speed local area networks, and fiber-optic links     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

A 60-GHz uniplanar MMIC 4/spl times/ subharmonic mixer

A uniplanar GaAs monolithic microwave integrated circuit /spl times/4 subharmonic mixer (SHM) has been fabricated for 60-GHz-band applications using an antiparallel diode pair in finite ground coplanar (FGC) waveguide technology. This mixer is designed to operate at an RF of 58.5-60.5 GHz, an IF of 1.5-2.5 GHz, and an LO frequency of 14-14.5 GHz. FGC transmission-line structures used in the mixer implementation were fully characterized using full-wave electromagnetic simulations and on-wafer measurements. Of several mixer configurations tested, the best results show a maximum conversion loss of 13.2 dB over the specified frequency range with a minimum local-oscillator power of 3 dBm. The minimum upper sideband conversion loss is 11.3 dB at an RF of 58.5 GHz and an IF of 2.5 GHz. This represents excellent performance for a 4/spl times/ SHM operating at 60 GHz.     

A 1-GHz CMOS up-conversion mixer

A high-frequency linear MOS mixer topology is presented for the implementation of a 1-GHz up-conversion mixer in a standard 0.7-μm CMOS technology. The high output bandwidth has been achieved by the development of an nMOS-only current amplifier that converts the modulated current of the nMOS mixing transistor biased in the linear region to the RF output voltage     

A 21-26-GHz SiGe bipolar power amplifier MMIC

A three-stage 21-26-GHz medium-power amplifier fabricated in f/sub T/=120 GHz 0.2 /spl mu/m SiGe HBT technology has 19 dB small-signal gain and 15 dB gain at maximum output power. It delivers 23 dBm, 19.75% PAE at 22 GHz, and 21 dBm, 13% PAE at 24 GHz. The differential common-base topology extends the supply to BV/sub CEO/ of the transistors (1.8 V). New on-chip components, such as onchip interconnects with floating differential shields, and self-shielding four-way power combining/dividing baluns provide inter-stage coupling and single-ended I/O interfaces at the input and output. The 2.45/spl times/2.45 mm/sup 2/ MMIC was mounted as a flipchip and tested without a heatsink.     

A compact, high-gain, 2-20-GHz MMIC amplifier

The authors describe an advanced MMIC amplifier providing a 20-dB gain block over the 2-20-GHz frequency range. The chip requires only three external bias capacitors and is well suited to automatic assembly. By simultaneously offering improved gain, power, and circuit density in the 2-20-GHz range, a significant advancement in single chip performance has been achieved     

9.5-14.5 GHz GaAs HBT 1W MMIC with 55% peak power added efficiency

A fully matched, broadband, high efficiency MMIC power amplifier using AlGaAs/GaAs HBTs has been designed and tested. At 7 V collector bias, this HBT amplifier produced 31 dBm CW peak output power with 9 dB gain and 55% peak power-added efficiency in the 9.5-14.5 GHz band. To the authors' knowledge, this is the highest efficiency ever achieved from a broadband MMIC power amplifier     

A low-power up-conversion CMOS mixer for 22-29-GHz ultra-wideband applications

A double-balanced, low-power, and low-voltage dual-gate up-conversion mixer working at K-band is designed and fabricated in the UMC 130-nm logic CMOS process. The mixer achieves a 3-dB conversion-gain bandwidth of 1.8 GHz at the input IF port and a 3-dB conversion-gain bandwidth of 10 GHz at the output RF port. The mixer achieves an output referred 1-dB compression point as high as -5.8 dBm and an output referred third-order intercept point as high as 5.8 dBm, while consuming 8.0 mW from a 1.2-V supply. This study demonstrates that the implementation of low-power mixers operating in the 22-29-GHz band for ultra-wideband automotive radar applications is possible in low-cost and low-voltage logic CMOS technology.     

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

A 2-V, low distortion, 1-GHz CMOS up-conversion mixer

A 1 GHz, very linear, CMOS up-conversion mixer is presented. The circuit is able to operate at a 2-V power supply. The topology has a true single-ended output stage which avoids the use of any balun. The total power consumption in both the mixers and the output stage is only 22 mW at 2 V. A profound analysis of the origins of distortion in the mixer has been performed. This study has resulted in the optimization of the linearity of the realized up-conversion mixer. The low power consumption, the low supply voltage, the high frequency performance, and the relatively large amplitude and low distortion single-ended off-chip output signal make the presented topology very suitable for wireless applications     

Gilbert multiplier as an active mixer with conversion gain bandwidth of up to 17 GHz

A monolithically integrated mixer based on a Gilbert cell multiplier for ultra-broadband applications has been produced in self-aligning 1 mu m silicon bipolar technology. Positive power conversion gain bandwidths for RF and LO up to 17.3 GHz and for the intermediate frequency (IF) up to 13 GHz were measured. The corresponding -3 dB frequencies are 9 GHz for RF and LO (IF=100 MHz) and 8 GHz (f/sub LO/=1 GHz) for IF.<>     

A low-noise fixed-tuned 300-360-GHz sub-harmonic mixer using planar Schottky diodes

This letter presents the design and fabrication of a low-noise fixed-tuned 300-360-GHz sub-harmonic mixer, featuring an anti-parallel pair of planar Schottky diodes fabricated by the University of Virginia and flip-chipped onto a suspended quartz-based microstrip circuit. The mixer exhibits a double side band (DSB) equivalent noise temperature lower than 900K over 18% of bandwidth (300-360-GHz), with 2 to 4.5mW of local oscillator (LO) power. At room temperature, a minimum DSB mixer noise temperature of 700K and conversion losses of 6.3dB are measured at 330GHz.     

一种偏置电流可控的2.4GHz SiGe HBT功率放大器设计

A 2.4-GHz SiGe HBT power amplifier （PA） with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of ＋3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respec- tively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32×1.37mm^2.     

A 2.4-GHz SiGe HBT power amplifier with bias current controlling circuit

A 2.4-GHz SiGe HBT power amplifier (PA) with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of 3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respectively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32 × 1.37 mm2.     

A 210-GHz fT SiGe HBT with a non-self-aligned structure

A record 210-GHz f_T SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA/μm² is fabricated with a new nonself-aligned (NSA) structure based on 0.18 μm technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f_T. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device     

A 24-GHz Patch Array with a Power Amplifier/Low-Noise Amplifier MMIC

This paper presents an active patch array designed at 24 GHz. It can be used as a front-end component for a phased array. A series resonant array structure is chosen which is compact and easy excite. With 5 elements, the array proved a 12-dB antenna gain. A power amplifier and a low noise amplifier are designed on a single GaAs chip (PALNA). Bias switch is used in the PALNA, which greatly reduces the switch loss in a transceiver and increases the efficiency. 20-dB small signal gain is achieved in both power amplifier and low noise amplifier. The active patch array is built by the combination of the patch array and PALNA. The measured active gain of this antenna is 35-dB for the PA mode and 31-dB for the LNA mode. This active patch array can obtain an EIRP of 34 dBm with a total radiated power of 22dBm and a maximum PAE of 32%. To check the noise performance, we applied sources at both normal temperature and 77K (liquid nitrogen) and extracted the noise figure (3.5 dB) of the active antenna by the Y factor method. The results proved that the active antenna is working efficiently as both a transmitting and receiving antenna.     

A subharmonic self-oscillating mixer with integrated antenna for60-GHz wireless applications

A balanced integrated-antenna self-oscillating mixer at 60 GHz is presented in this paper. The modal radiation characteristics of a dual-feed planar quasi-Yagi antenna are used to achieve RF-local oscillator (RF-LO) isolation between closely spaced frequencies. The balanced mixer is symmetric, inherently broad band, and does not need an RF balun. Pseudomorphic high electron-mobility transistors are used in a 30-GHz push-pull circuit to generate the second harmonic and a 30-GHz dielectric resonator was used to stabilize the fundamental oscillation frequency. This allows the possibility of building a balanced low-cost self-contained antenna integrated receiver with low LO leakage for short-range narrow-band communication. Phase locking can be done with half of the RF frequency. The circuit exhibits a conversion loss less than 15 dB from 60 to 61.5 GHz, radiation leakage of -26 dBm at 60 GHz, and IF phase noise of -95 dBc/Hz at 100-kHz offset     

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

A CMOS four-quadrant analog multiplier with single-ended voltageoutput and improved temperature performance

An all-MOS, four-quadrant analog multiplier with single-ended voltage output and good temperature performance is presented. It is based on a linear MOS transconductor with extended operation range to four quadrants and on a linear MOS resistor. The temperature behavior of the multiplier is improved by a factor of 10. The multiplier was realized using a 3-μm p-well self-aligned contact CMOS (SACMOS) process. A linearity better than 1% for each of the input voltages of 5 V_p-p, a bandwidth from DC to 1.2 MHz, and output noise 73 dB below full scale were achieved. The active chip area is 210 mil² and power consumption is 6 mW. A new approach for implementing a temperature-independent analog multiplier is proposed