A two-dimensional analytical model of the cross-bridge Kelvin resistor

This paper presents an analytical model which correctly explains the two-dimensional (2-D) current-crowding effects observed in the cross-bridge Kelvin resistor (CBKR). The model explains that the kelvin resistance measured by this device consists of two components, one due to specific resistivity and the other due to current flowing in the overlap region between the contact and the diffusion edges. The geometrical dependence of this second component is derived analytically and compared with two-dimensional numerical simulations. It becomes significant when specific contact resistivityrho_{c} < R_{s} times delta^{2}, where δ is the amount of overlap between edge of the contact and the edge of the diffusion path, and Rsis the diffusion sheet resistance.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

An optimized bidirectional lightning surge protection semiconductordevice

This paper addresses the analysis of a bidirectional lightning surge protection power semiconductor device called the bidirectional breakover diode (BBD). The BBD has a high-speed response, high current capability, and low conduction and switching losses. The influence of the layout on the trigger and holding current values has been studied by means of two-dimensional (2-D) electrical simulations. The length of the peripheral N⁺ diffusion together with the location of the edge contact between the metallization and the P⁺/N⁺ diffusions are crucial in optimizing the trigger mechanism and the trigger and holding current values. The turn on of the inner cells has also been analyzed by numerical simulations, showing the effect of the central parasitic P⁺NP⁺ bipolar transistor at the initial phase of the turn on process. Experimental results have been obtained from fabricated 180-V BBD devices with holding current values in the range of 150-250 mA. The BBD surge protection capability has been corroborated by impulsive tests using a 10/1000 μs, 50 A, 1000 V, current pulse. In addition, transient losses have been monitored in order to improve the surge protection capability of the device. Finally, the static and dynamic BBD thermal behaviour has also been analyzed     

An analysis of the difference in behavior of top and bottom contact organic thin film transistors using device simulation

This paper presents a systematic analysis of an already reported phenomenon, namely, the difference in device performance of top and bottom contact organic thin film transistors (OTFT) by combining experiments and two-dimensional device simulations. The mobility of the as measured devices in the bottom contact OTFT is found to be lower by two orders of magnitude than the top contact structure, which is generally attributed to the higher metal-semiconductor contact resistance in the bottom contact devices due to lower contact area. However, we found that this large mobility difference exists even after correcting for the metal-semiconductor contact resistance through transfer line method (TLM). This result suggests that structural differences are playing a dominant role in lowering down the performance of bottom contact devices. This effect is then systematically investigated through two-dimensional physics-based numerical simulations by considering several structural inhomogenities around the contacts. The main reason for such an occurrence is attributed to the poor morphology (or comparatively low mobility) of pentacene films around the source/drain electrodes in the bottom contact devices. Finally, we also show a reasonable match between the simulated and experimental device characteristics, enabling calibration of the simulator for further use in design of OTFTs.     

An energy-dependent two-dimensional substrate current model for thesimulation of submicrometer MOSFET's

A multicurrent contour, average-energy-based, substrate current model for silicon submicrometer NMOSFETs is presented as a significant improvement to the local-field model that is commonly used in modern drift-diffusion device simulators. The model is implemented as a post-processor by applying a one-dimensional energy conservation equation to many current contours in order to generate a two-dimensional representation of average energy and impact ionization rate which is integrated to calculate the substrate current. Comparisons of simulations and experimental I-V curves for both simple and LDD MOSFETs are presented. Outstanding agreement has been obtained over a wide range of bias conditions and channel lengths     

Direct Moat Isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird's beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 /spl mu/m.     

Effect of bipolar turn-on on the static current-voltagecharacteristics of scaled vertical power DMOSFET's

The parasitic bipolar transistor inherent in the power vertical Double Diffused MOSFET (DMOSFET) structure can have a significant impact on its performance and reliability. Selectively formed TiSi₂ films on source contacts were used to reduce the contact resistance to n ⁺ source diffusion. These devices exhibit “kinks” in the output I-V characteristics. High contact resistance of TiSi₂ to moderately doped p-body diffusion causes high output conductance. Detailed two-dimensional numerical simulations are used to investigate the effect of the parasitic bipolar transistor on the static characteristics of scaled silicided DMOSFET's. The high contact resistance of TiSi₂-p-body interface leads to a floating potential and causes significant reduction in the MOS gate threshold voltage and results in a premature bipolar turn-on. It is shown that the parasitic bipolar turn-on places an important constraint on the scalability of the device into the submicron regime. A novel self-aligned DMOSFET structure with a shallow diffused p⁺ region is shown to eliminate this effect. Numerical simulations are shown to be in excellent agreement with the measured data at various temperatures     

Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices.     

Design and analysis of heterojunction bipolar transferred electrondevices

The design of the heterojunction bipolar transferred electron device (HBTED) is considered. MOCVD-grown AlGaAs/GaAs HBTEDs were fabricated and 60 GHz operation was confirmed by on-wafer measurements. Analysis of the device operation is aided by the use of Monte Carlo device simulations, equivalent circuit model simulations and two-dimensional (2-D) drift-diffusion model simulations and the simulation results are compared with measurements on the fabricated HBTEDs and HBTED test structures. The effects of the external base-collector region and current spreading in the collector region are investigated and the latter is found to be of great importance. Our simulations show that having an appropriately graded collector doping profile can compensate the current spreading and this hypothesis is supported by measurement results. Conclusions are drawn regarding the design of practical HBTEDs for mm-wave oscillator applications     

Current confinement and leakage currents in planarburied-ridge-structure laser diodes on n-substrate

An electrical device model for the planar buried-ridge-structure laser on n-type substrate is discussed. It takes into account the finite p-type contact resistivity, the two-dimensional current spreading, and the electron leakage current by drift and diffusion. Using this model, the influence of the relevant device parameters on the leakage current in InGaAsP/InP devices emitting at 1.3 μm is investigated. It is shown that leakage currents are negligible at room temperature if the contact stripe width does not exceed the sum of the active region width and the p-type confinement layer thickness, but they increase markedly with broader contact stripes and with contact resistivities above 10^-5 Ω-cm². The most important parameter influencing the leakage currents is the doping level of the P-InP confinement layer. With a p-type doping level of 1×10¹⁸ cm^-3, a p-type contact resistivity below 10^-5 Ω-cm² and a contact stripe width of 6 μm, the model calculations predict a maximum operation temperature exceeding 100°C. This agrees fairly well with experimental data proving that the rather simple planar buried-ridge-structure laser performs as well as more sophisticated devices incorporating current-blocking layers     

Electrical isolation design rule for GaAs integrated circuitsfabricated on semi-insulating substrates

The characteristics of n-semi-insulating-n (n-si-n) structures that dictate the design rules for electrical isolation between active devices of GaAs integrated circuits fabricated on semi-insulating substrates are studied by one-dimensional and two-dimensional numerical simulations. It is found that the I-V characteristics of these structures are characterized by sharp current-rising regions which result from a potential barrier lowering effect caused by the punchthrough phenomenon. Simplified expressions are derived for quick evaluation of the punchthrough voltages for both one-dimensional and two-dimensional analyses. For a given operating voltage, the one-dimensional calculation gives a larger spacing between n regions in a n-si-n structure for onset of large current flow than does the two-dimensional analysis. Therefore, the spacing obtained from one-dimensional results can be used as a conservative design criterion for device isolation. For more aggressive electrical isolation design, two-dimensional simulation is necessary since it provides more accurate results     

Demonstration of the importance of the oxide breakup inpolysilicon-contacted-emitter modeling

The authors demonstrate theoretically a very rapid increase in the ideal base current of poly-contacted-emitter bipolar transistors with the fraction of the interface which has realigned with the single-crystalline substrate. Polysilicon contacts have played an integral role in reducing device dimensions and increasing the gain of bipolar transistors for some time. However, the mechanism by which the gain (β) enhancement occurs is still not fully understood. Simulations were performed for a device with a transparent emitter using the simulation tool DAP2D (device analysis program in two dimensions) to model the effect on the base current of the breaking up of the oxide layer between the poly contact and the emitter. The simulations show that for poly contacts typical of VLSI applications, the modeled dependence of the base current on the percentage of the oxide interface which is broken up correlates well with experimental results     

RECIPE—A two-dimensional VLSI process modeling program

REnsselaer Computer integrated Circuits Process Engineering (RECIPE) is a two-dimensional (2-D) integrated circuit process modeling program developed for use in VLSI applications. The program incorporates a 2-D diffusion model which includes the concentration dependence of the diffusion coefficients. An incremental solution method is used to compute the appropriate diffusion coefficients as a function of impurity concentration throughout space. RECIPE also incorporates a 2-D ion-implantation model. While intended as a general-purpose modeling program, RECIPE has been used to study channel-length decrease of short-channel MOSFET's during high-temperature processing. A typical phosphorus-implanted (150 keV, 10¹⁶/cm²) 1-µm gate transistor had no channel after processing for 60 min at 1000°C, while an arsenic-implanted device had an effective channel length of ∼ 0.1 µm after similar processing.     

The effect of base-Schottky geometry on Si PBT device performance

Experimental device results are compared with two-dimensional numerical simulations of etched-groove Si permeable base transistors (PBT's). Both the simulations and experimental devices indicate that small variations in the metal-semiconductor contact area of the base fingers can lead to substantial (≥ 50-percent) deviations in key device parameters such as transconductance Gm, threshold voltage VT, and intrinsic input capacitance Cin. In spite of these variations, the maximum small-signal short-circuit unity-current-gain frequency fTdoes not change significantly because the maximum ratio of Gmto Cinremains nearly constant. In the experimental devices, fTis limited to about 40 percent of the predicted value due to parasitic capacitances (e.g., base pad capacitance).     

Direct moat isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird's beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 µm.     

Two-dimensional analysis of ion-implanted, bipolar-compatible,long- and short-channel junction field-effect transistors

A two-dimensional analysis of ion-implanted, bipolar-compatible, long- and short-channel JFETs is presented. The two-dimensional device simulator PISCES is used to study the steady-state characteristics. The linear and saturation regions are analyzed, and insight about the transition region between them is obtained. Short-channel JFET behavior deviates considerably from the conventional theory developed based on the gradual channel approximation, because the x-direction electric field in the channel of the short-channel JFET is much stronger than that in the long-channel JFET. The study shows that the short-channel JFET has several properties that were not previously emphasized: (a) no pinch-off in saturation operation: (b) free-carrier drift velocity saturates in saturation operation: and (c) power-law I-V characteristics in the cutoff region. Details regarding the shape of the conducting channel, the electric field vectors, the current vectors, and the current-voltage characteristics are provided     

Two-dimensional charge-control model for MODFET's

A dc model for MODFET's accounting for two-dimensional effects is proposed. In this model, charge control is realized by solving the two-dimensional Poisson equation in the depleted AlGaAs region. The transport picture used for the two-dimensional electron gas (2-DEG) in the AlGaAs/GaAs heterojunction relies on the quasi-Fermi level together with a field-dependent mobility and therefore includes 2-DEG diffusion effects. Our approach reduces the analysis to a single integral equation.I-Vcurves, which provide a good fitting to the reported experimental data, are obtained using a smooth velocity-field curve. The channel voltage, 2-DEG concentration, parallel electric-field, and drift velocity along the channel are given in this study and provide a clear picture of current saturation. The model is consistent with the approximate two-region saturation picture but provides a smoother transition. We observe a large diffusion current component along the channel in addition to the drift current. However, the total saturation current obtained has nearly the same value as found from the two-region model. This new model with two-dimensional charge control provides much insight into the current saturation mechanism of the MODFET.     

The circular resistor (CR)-a novel structure for the analysis ofVLSI contacts

The circular resistor, a structure for extracting metal-semiconductor contact resistivity, is discussed. A two-dimensional analytical solution of the system is shown in a simplified case; the complex solution is calculated by numerical simulations. Very good agreement between the two solutions was found. Regarding resolution, the circular resistor exhibits characteristics similar to those of other standard structures, but the circular shape fits the actual geometry of VLSI contacts     

Transient characteristics of n-channel hybrid Schottky injectionFETs

Theoretical transient characteristics of hybrid Schottky injection FETs (HSINFETs) are considered. The theoretical analysis is based on two-dimensional numerical simulations, in which the entire turn-off process and the effects of minority-carrier injection levels on the transient performance of the HSINFET device are analyzed. The analysis shows that the fast turn-off speed in the HSINFET device occurs because (1) only a small number of minority carriers is injected into the drift region, (2) a current path, provided by the Schottky contact, effectively removes electrons from the drift region during turn-off, and (3) Schottky clamping at the anode is effective during turn-off and prevents the p⁺ portion of the hybrid anode from significantly injecting holes. Experimental results compared the DC and transient performance of the lateral double-diffused MOS transistor (LDMOST), lateral insulated-gate transistor (LIGT), Schottky injection field-effect (SINFET), and HSINFET are presented     

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n⁺-p⁺ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm