Effect of polyimide baking on bump resistance in flip-chip solder joints

The effect of polyimide (PI) thermal process on the bump resistance of flip-chip solder joint is investigated for 28 nm technology device with aggressive extreme low-k (ELK) dielectric film scheme and lead-free solder. Kelvin structure is designed in the bump array to measure the resistance of single solder bump. An additional low-temperature pre-baking before standard PI curing increases the bump resistance from 9.3 mΩ to 225 mΩ. The bump resistance increment is well explained by a PI outgassing model established based on the results of Gas Chromatography–Mass Spectrophotometer (GC–MS) analysis. The PI outgassing substances re-deposit on the Al bump pad, increasing the resistance of interface between under-bump metallurgy (UBM) and underneath Al pad. The resistance of interface is twenty-times higher than pure solder bump, which dominates the measured value of bump resistance. Low-temperature plasma etching prior to UBM deposition is proposed to retard the PI outgassing, and it effectively reduces the bump resistance from 225 mΩ to 10.8 mΩ.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Geometrical effect of bump resistance for flip-chip solder joints: Finite-element modeling and experimental results

The bump resistance of flip-chip solder joints was measured experimentally and analyzed by the finite-element method. Kelvin structures for flip-chip solder joints were designed and fabricated to measure the bump resistance. The measured value was only about 0.9 mΘ at room temperature, which was much lower than that expected. Three-dimensional (3-D) modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 mΘ, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and a significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during the electromigration of flip-chip solder joints.     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Interfacial reaction and joint reliability of fine-pitch flip-chip solder bump using stencil printing method

This study was focused on the formation and reliability evaluation of solder joints with different diameters and pitches for flip chip applications. We investigated the interfacial reaction and shear strength between two different solders (Sn-37Pb and Sn-3.0Ag-0.5Cu, in wt.%) and ENIG (Electroless Nickel Immersion Gold) UBM (Under Bump Metallurgy) during multiple reflow. Firstly, we formed the flip chip solder bumps on the Ti/Cu/ENIG metallized Si wafer using a stencil printing method. After reflow, the average solder bump diameters were about 130, 160 and 190 μm, respectively. After multiple reflows, Ni₃Sn₄ intermetallic compound (IMC) layer formed at the Sn-37Pb solder/ENIG UBM interface. On the other hand, in the case of Sn-3.0Ag-0.5Cu solder, (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ IMCs were formed at the interface. The shear force of the Pb-free Sn-3.0Ag-0.5Cu flip chip solder bump was higher than that of the conventional Sn-37Pb flip chip solder bump.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Effect of Al trace dimension on electromigration failure time of flip-chip solder joints

The effect of Al-trace dimension on electromigration of flip-chip solder joints was investigated. The Al trace dimension was found to have a significant influence on the electromigration failure time. When joints with Al traces 100 μm wide were stressed by 1.0 A at 100°C, failure times were 35 h, 1,700 h, and >3,000 h for joints with Al traces that were 2,550 μm, 1,700 μm, and 850 μm long, respectively. Solder joints with Al traces 40 μm wide and 2,550 μm long failed instantly at 0.6 A. The Joule heating effect was found to be responsible for the huge difference in failure time.     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Isothermal aging effects on the microstructure and solder bump shear strength of eutectic Sn37Pb and Sn3.5Ag solders

The reliability of the eutectic Sn37Pb (63%Sn37%Pb) and Sn3.5Ag (96.5%Sn3.5%Ag) solder bumps with an under bump metallization (UBM) consisting of an electroless Ni(P) plus a thin layer of Au was evaluated following isothermal aging at 150 °C. All the solder bumps remained intact after 1500 h aging at 150 °C. Solder bump microstructure evolution and interface structure change during isothermal aging were observed and correlated with the solder bump shear strength and failure modes. Cohesive solder failure was the only failure mode for the eutectic Sn37Pb solder bump, while partial cohesive solder failure and partial Ni(P) UBM/Al metallization interfacial delamination was the main failure mode for eutectic Sn3.5Ag solder bump.     

Effect of Cu stud microstructure and electroplating process onintermetallic compounds growth and reliability of flip-chip solder bump

In electroplating-based flip-chip technology, the Cu stud and solder deposition processes are two of the most important factors affecting the reliability of solder joints. The growth of Cu-Sn intermetallic compounds (IMC) also plays a critical role. In this paper, the effect of Cu stud surface roughness and microstructures on the reliability of solder joint was studied. The surface roughness of the Cu stud was increased as the Cu electroplating current density increased. The microstructural morphology of the Cu-Sn IMC layer was affected by Cu stud surface structure. We found the growth rate of IMC layer increased with the increasing of Cu stud grain size and surface roughness during aging test. The growth kinetics of Cu-Sn intermetallic compound formation for 63Sn/37Pb solder followed the Arrhenius equation with activation energy varied from 0.78 eV to 1.14 eV. The ratios of Cu₃ Sn layer thickness to the total Cu-Sn IMC layer thickness was in the range of 0.5 to 0.15 for various Cu microstructures at 150°C during thermal aging test. The shear strength of solder bump was measured after thermal aging and temperature/humidity tests. The relationship between electroplating process and reliability of solder joints was established. The failure mode of solder joints was also analyzed     

Cross-interaction of under-bump metallurgy and surface finish in flip-chip solder joints

The cross-interaction of the under-bump metallurgy (UBM)/solder interface and the solder/surface-finish interface in flip-chip solder joints was investigated. In this study, the UBM on the chip side was a single layer of Cu (8.5 μm), and the surface finish on the substrate side was a 0.2-μm Au layer over 5-μm Ni. It was shown that, after two reflows, the Ni layer of the surface finish had been covered with (Cu_1−xNi_x)₆Sn₅. This shows that the effect of cross-interaction of the two interfaces is important even during the reflow stage. During subsequent solid-state aging at 115°C, 135°C, and 155°C, the formation of (Cu_1−xNi_x)₆Sn₅ over the Ni layer was found to have the effect of reducing the Ni consumption rate. At the same time, the Cu consumption rate of the UBM was accelerated. The results of this study show that the selection of the UBM and the surface finish has to be considered together because the cross-interaction of the two interfaces plays an important role.     

Residual stress and interfacial reaction of the electroplated Ni-Cu alloy under bump metallurgy in the flip-chip solder joint

Pure Ni, the Ni-Cu alloy, and pure Cu layers as the under bump metallurgy (UBM) for a flip-chip solder joint were deposited by electrolytic plating. For the pure Ni layer, residual stress can be controlled by adding a wetting agent and decreasing current density, and it is always under tensile stress. The Ni-Cu alloys of different Cu compositions from ∼20wt.%Cu to 100wt.%Cu were deposited with varying current density in a single bath. The residual stress was a strong function of current density and Cu composition. Decreasing current density and increasing Cu content simultaneously causes the residual stress of the metal layers to sharply decrease. For the pure Cu layer, the stress is compressive. The Cu layer acts as a cushion layer for the UBM. The residual stress of the UBM strongly depends on the fraction of the Cu cushion layer. Interfacial reaction of the UBM with Sn-3.5 wt.% Ag was studied. As the Cu contents of Ni-Cu alloys increased, the dissolution rate increased. Several different intermetallic compounds (IMCs) were found. The lattice constants of alloys and the IMC increase with increasing Cu contents because the larger Cu atoms substitute for the smaller Ni atoms in the crystallites. The Cu content of the IMC are strongly dependent on the composition of the alloys. Ball shear tests were done with different metal-layer schemes. The failure occurs through the IMC and solder.     

Mechanism of interfacial reaction for the Sn-Pb solder bump with Ni/Cu under-bump metallization in flip-chip technology

Nickel-based under-bump metallization (UBM) has been widely used in flip-chip technology (FCT) because of its slow reaction rate with Sn. In this study, solder joints after reflows were employed to investigate the mechanism of interfacial reaction between the Ni/Cu UBM and eutectic Sn-Pb solder. After deliberate quantitative analysis with an electron probe microanalyzer (EPMA), the effect of Cu content in solders near the interface of the solder/intermetallic compound (IMC) on the interfacial reaction could be probed. After one reflow, only one layered (Ni_1−x,Cu_x)₃Sn₄ with homogeneous composition was found between the solder bump and UBM. However, after multiple reflows, another type of IMC, (Cu_1−y,Ni_y)₆Sn₅, formed between the solder and (Ni_1−x,Cu_x)₃Sn₄. It was observed that if the concentration of Cu in the solders near the solder/IMC interface was higher than 0.6 wt.%, the (Ni_1−x,Cu_x)₃Sn₄ IMC would transform into the (Cu_1−y,Ni_y)₆Sn₅ IMC. The Cu contents in (Ni_1−x,Cu_x)₃Sn₄ were altered and not uniformly distributed anymore. With the aid of microstructure evolution, quantitative analysis, elemental distribution by x-ray color mapping, and related phase equilibrium of Sn-Ni-Cu, the reaction mechanism of interfacial phase transformation between the Sn-Pb solder and Ni/Cu UBM was proposed.     

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×10³ A/cm² at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.     

Microstructure and shear strength evolution of SnAg/Cu surface mount solder joint during aging

The effect of aging at 150°C on the microstructure and shear strength of SnAg/Cu surface mount solder joint has been investigated with comparison to 62Sn36Pb2Ag/Cu. It is found that the diffusion coefficient of intermetallic compounds at SnAg/Cu interface is smaller than that of intermetallic compounds at SnPbAg/Cu interface at 150°. The shear strength of SnAg solder joint is higher and decreases at a smaller rate during aging compared to that of SnPbAg solder joint. The fracture surface analysis shows that as the aging time increases, the fracture takes place along the solder/Cu₆Sn₅ interface with an extension toward the Sn−Cu intermetallic layer.     

Intermetallic compound formation and morphology evolution in the 95Pb5Sn flip-chip solder joint with Ti/Cu/Ni under bump metallization during reflow soldering

Intermetallic compound formation and morphology evolution in the 95Pb5Sn flip-chip solder joint with the Ti/Cu/Ni under bump metallization (UBM) during 350°C reflow for durations ranging from 50 sec to 1440 min were investigated. A thin intermetallic layer of only 0.4 μm thickness was formed at the 95Pb5Sn/UBM interface after reflow for 5 min. When the reflow was extended to 20 min, the intermetallic layer grew thicker and the phase identification revealed the intermetallic layer comprised two phases, (Ni,Cu)₃Sn₂ and (Ni,Cu)₃Sn₄. The detection of the Cu content in the intermetallic compounds indicated that the Cu atoms had diffused through the Ni layer and took part in the intermetallic compound formation. With increasing reflow time, the (Ni,Cu)₃Sn₄ phase grew at a faster rate than that of the (Ni,Cu)₃Sn₂ phase. Meanwhile, irregular growth of the (Ni,Cu)₃Sn₄ phase was observed and voids formed at the (Ni,Cu)₃Sn₂/Ni interface. After reflow for 60 min, the (Ni,Cu)₃Sn₂ phase disappeared and the (Ni,Cu)₃Sn₄ phase spalled off the NI layer in the form of a continuous layer. The gap between the (Ni,Cu)₃Sn₄ layer and the Ni layer was filled with lead. A possible mechanism for the growth, disappearance, and spalling of the intermetallic compounds at the 95Pb5Sn/UBM interface was proposed.     

Soldering-induced Cu diffusion and intermetallic compound formation between Ni/Cu under bump metallization and SnPb flip-chip solder bumps

Nickel-based under bump metallization (UBM) has been widely used as a diffusion barrier to prevent the rapid reaction between the Cu conductor and Sn-based solders. In this study, joints with and without solder after heat treatments were employed to evaluate the diffusion behavior of Cu in the 63Sn-37Pb/Ni/Cu/Ti/Si₃N₄/Si multilayer structure. The atomic flux of Cu diffused through Ni was evaluated from the concentration profiles of Cu in solder joints. During reflow, the atomic flux of Cu was on the order of 10¹⁵–10¹⁶ atoms/cm²s. However, in the assembly without solder, no Cu was detected on the surface of Ni even after ten cycles of reflow. The diffusion behavior of Cu during heat treatments was studied, and the soldering-process-induced Cu diffusion through Ni metallization was characterized. In addition, the effect of Cu content in the solder near the solder/intermetallic compound (IMC) interface on interfacial reactions between the solder and the Ni/Cu UBM was also discussed. It is evident that the (Cu,Ni)₆Sn₅ IMC might form as the concentration of Cu in the Sn-Cu-Ni alloy exceeds 0.6 wt.%.     

The effect of intermetallic compound morphology on Cu diffusion in Sn-Ag and Sn-Pb solder bump on the Ni/Cu Under-bump metallization

The eutectic Sn-Ag solder alloy is one of the candidates for the Pb-free solder, and Sn-Pb solder alloys are still widely used in today’s electronic packages. In this tudy, the interfacial reaction in the eutectic Sn-Ag and Sn-Pb solder joints was investigated with an assembly of a solder/Ni/Cu/Ti/Si₃N₄/Si multilayer structures. In the Sn-3.5Ag solder joints reflowed at 260°C, only the (Ni_1−x,Cu_x)₃Sn₄ intermetallic compound (IMC) formed at the solder/Ni interface. For the Sn-37Pb solder reflowed at 225°C for one to ten cycles, only the (Ni_1−x,Cu_x)₃Sn₄ IMC formed between the solder and the Ni/Cu under-bump metallization (UBM). Nevertheless, the (Cu_1−y,Ni_y)₆Sn₅ IMC was observed in joints reflowed at 245°C after five cycles and at 265°C after three cycles. With the aid of microstructure evolution, quantitative analysis, and elemental distribution between the solder and Ni/Cu UBM, it was revealed that Cu content in the solder near the solder/IMC interface played an important role in the formation of the (Cu_1−y,Ni_y)₆Sn₅ IMC. In addition, the diffusion behavior of Cu in eutectic Sn-Ag and Sn-Pb solders with the Ni/Cu UBM were probed and discussed. The atomic flux of Cu diffused through Ni was evaluated by detailed quantitative analysis in an electron probe microanalyzer (EPMA). During reflow, the atomic flux of Cu was on the order of 10¹⁶−10¹⁷ atoms/cm²sec in both the eutectic Sn-Ag and Sn-Pb systems.     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.