A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption.     

一种用于数字功放的低功耗宽输入电压比较器

设计了一种适用于数字功率放大器应用的全差分低功耗宽输入CMOS电压比较器.采用TSMC 0.18μm/3.3V CMOS工艺模型,用Cadence软件进行模拟仿真,比较器低频增益81.2dB,输入共模电压范围1.4~3.3V,整个电路的静态功耗仅248.6μW.运用该结构的比较器具有较低的失调电压,大幅度提高了比较器的精度;较宽的输入共模电压范围及低功耗,可用于数字功放等高性能模拟IP模块的设计.     

用于脑电信号记录的低噪声低功耗放大器

为了满足脑电信号(EEG)记录阵列的应用需求,设计了一种全差分的低噪声、低功耗放大器电路.该电路利用亚阈值区晶体管作为伪电阻,与输入电容和反馈电容形成高通通路,有效抑制了输入信号的直流失调电压,无需片外隔直电容,实现了电路的全集成.放大器中的跨导放大器(OTA)采用亚阈值晶体管进行设计,实现了较大的输出摆幅、良好的功耗和噪声性能.放大器电路采用SMIC 130 nm 1P8M混合信号工艺实现,芯片面积0.6 mm2.测试结果表明,在电源电压0.6V时,放大器可处理信号带宽为10 Hz～7 kHz,等效输入噪声的均方根值为3.976 μV,噪声有效因子为3.658,总功耗仅为2.4 μW.     

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.     

Low-Power Log-Domain CMOS Filter Bank for 2-D Sound Source Localization

This paper proposes the design of a novel current-mode front-end for the extraction of localization spectral cues from two audio signals, together with test results. The front-end consists of two parallel filter banks, envelope extraction and comparison circuitry, together with an AGC loop. The extracted cues are intended to be further processed in order to determine the source azimuth and elevation. A current-mode log-domain implementation using subthreshold MOS operation is used for micropower operation while still achieving a good bandwidth and linearity. A current-mode solution is also preferred because of the ease of implementation of certain mathematical operations. The front-end splits the input signals into different frequency bands and computes monaural and interaural spectral cues from the resulting signal envelopes for each band. The front-end has been optimized to operate at a supply voltage of 1.8 V and most blocks have been designed using a differential architecture. To our knowledge, this is the first log-domain implementation of a front-end for 2-D localization cues extraction. The design has been carried out using a standard double-poly double-metal 0.8 m CMOS process with V _T = 0.8 V. The bandpass filters which form the main core of the chip exhibit a measured dynamic range of 62 dB corresponding to 1.9% THD, while the total power dissipation is 890 W.     

A Very Low Voltage Bipolar Op-Amp for Sensor Applications

A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm², has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported.     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

A Low-Voltage Low-Power Rail-to-Rail Constant g m Transconductance Amplifier

In this paper, a low-voltage low-power rail-to-rail constant g _m transconductance amplifier (TA) is introduced. The supply voltages are set at (±1.5 V). The circuit depends on selecting the maximum transconductance (g _m ) to achieve an almost constant g _m over the entire common-mode (CM) range. The circuit is then used to realize a second-order 4 MHz lowpass filter consuming 530 W, and a fifth-order 450 kHz lowpass elliptic filter consuming 2.3 mW. Both filters can be integrated on silicon without any external connections.     

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 W, it has a sufficient input range, whereas conventional Wang's OTA needs 703 W to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.     

一种基于动态阈值NMOS管的1．2V模拟乘法器

基于CSMC0．6μm DPDM CMOS工艺进行设计,利用4个动态闽值NMOS和2个有源电阻实现了一种1．2V低功耗模拟乘法器电路,既节省了输入晶体管数目,又节省了偏置晶体管和偏置电路．1．2V模拟乘法器的输入信号VinA的频率为5MHz,信号峰峰值为1．0V,输入信号VinB的频率为100MHz,信号峰峰值为0．5V时,输出信号Vout的峰峰值为0．35V,一次谐波和三次谐波的差值为40dB．1．2V模拟乘法器输出信号的频带宽度为375MHz,平均电源电流约为30μA,即动态功耗约为36μw,适合于便携式电子产品和带宽要求不太高（400MHz以下）的场合．     

1 V低功耗套筒式CMOS运算放大器的设计

介绍了一种用于低电压CMOS模拟集成电路设计的阈值调节思想。利用该思想,在0.35μm标准CMOS工艺条件下,设计出电源电压仅为1 V的套筒结构集成运算放大器(Tele-scopic OPA)。HSPICE仿真表明,与传统结构相比,新型结构在保证增益、带宽等放大器重要指标的基础上,功耗有了显著的降低。     

低功耗的巴特沃思复数滤波器设计

总结了复数域内的信号处理原理,并介绍了应用于GPS射频前端的低功耗巴特沃思复数滤波器设计实现.该滤波器工作电压为1.5 V,功耗小于1 mW.性能指标为:中心频率4 MHz,3 dB带宽为3 MHz,偏离中心频率1 MHz以内的通带纹波小于0.5 dB,镜像频率处的抑制比为70 dB以上.最后在0.18 μm工艺下实现版图面积为0.5×0.48 mm2.     

Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

This paper describes a CMOS power amplifier with rail-to-rail input and output, also suitable for low voltage applications. The amplifier uses Simple Miller Compensation with high bandwidth stage to robustly and power efficiently compensate the amplifier. Circuit also includes a common mode adapter block, based on resistive level shift network, to implement rail-to-rail input and optional adaptive biasing block, which can be used to extend bandwidth of the amplifier for large high frequency inputs in continuous-time applications. Measurement results show that the amplifier is capable of driving heavy resistive and capacitive loads having maximum output current exceeding 100 mA, when driving 1 nF ‖ 10 Ω load from 3.0 V supply. Without adaptive biasing the linear amplifier achieves 5.7 MHz unity gain frequency and 61^∘ phase margin when driving 1 nF ‖ 1 kΩ load, while drawing 2.4 mA from 1.5 V supply.     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

单电容米勒补偿三级运放设计

为了满足低压电路的工作要求,我们设计了一种新型的三级运放.该运放采用单电容米勒补偿与交叉多径嵌套补偿结合的方法,利用前馈通路在左半平面形成的零点来补偿其在主通路中的极点.通过使用TSMC 0.18μm工艺仿真.仿真结果表明:该运放能够获得113 dB的增益.有着87°的相位裕度,在1.8 V电源电压和120 pF负债的情况下.整体功耗只有0.534 mW.由此可见,这种新型的补偿方式能够有效地对运放进行补偿,并且使运放获得较高的增益以及较大相位裕度.     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

一种0.8V低功耗低相位噪声锁相环的设计

本文提出了一种低电压应用的低功耗、低相位噪声锁相环（PLL）。其中压控振荡器（VCO）的工作电压为0.5V,其他模块的工作电压为0.8V。为了适应极低电压下的应用,文中振荡器采用了纯NMOS差分拓扑结构,鉴频鉴相器（PFD）采用改进的预充电结构,而电荷泵（CP）采用新型负反馈结构。预分频电路采用扩展的单相时钟逻辑电路构成,它可以工作在较高的频率下,节省了芯片面积和功耗。此外还采用了去除尾电流源等设计方法来降低相位噪声。采用SMIC 0.13μm RF CMOS工艺,在0.8V电源电压下,测得在整个锁定范围内,最差相位噪声为-112.4dBc/Hz@1MHz,其输出频率范围为3.166~3.383GHz。改进的PFD和新型CP功耗仅为0.39mW,占据的芯片面积仅100μm×100μm。芯片总面积为0.63mm2,在0.8V电源电压下功耗仅为6.54mW 。