A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption.     

一种用于数字功放的低功耗宽输入电压比较器

设计了一种适用于数字功率放大器应用的全差分低功耗宽输入CMOS电压比较器.采用TSMC 0.18μm/3.3V CMOS工艺模型,用Cadence软件进行模拟仿真,比较器低频增益81.2dB,输入共模电压范围1.4~3.3V,整个电路的静态功耗仅248.6μW.运用该结构的比较器具有较低的失调电压,大幅度提高了比较器的精度;较宽的输入共模电压范围及低功耗,可用于数字功放等高性能模拟IP模块的设计.     

用于脑电信号记录的低噪声低功耗放大器

为了满足脑电信号(EEG)记录阵列的应用需求,设计了一种全差分的低噪声、低功耗放大器电路.该电路利用亚阈值区晶体管作为伪电阻,与输入电容和反馈电容形成高通通路,有效抑制了输入信号的直流失调电压,无需片外隔直电容,实现了电路的全集成.放大器中的跨导放大器(OTA)采用亚阈值晶体管进行设计,实现了较大的输出摆幅、良好的功耗和噪声性能.放大器电路采用SMIC 130 nm 1P8M混合信号工艺实现,芯片面积0.6 mm2.测试结果表明,在电源电压0.6V时,放大器可处理信号带宽为10 Hz～7 kHz,等效输入噪声的均方根值为3.976 μV,噪声有效因子为3.658,总功耗仅为2.4 μW.     

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.     

Low-Power Log-Domain CMOS Filter Bank for 2-D Sound Source Localization

This paper proposes the design of a novel current-mode front-end for the extraction of localization spectral cues from two audio signals, together with test results. The front-end consists of two parallel filter banks, envelope extraction and comparison circuitry, together with an AGC loop. The extracted cues are intended to be further processed in order to determine the source azimuth and elevation. A current-mode log-domain implementation using subthreshold MOS operation is used for micropower operation while still achieving a good bandwidth and linearity. A current-mode solution is also preferred because of the ease of implementation of certain mathematical operations. The front-end splits the input signals into different frequency bands and computes monaural and interaural spectral cues from the resulting signal envelopes for each band. The front-end has been optimized to operate at a supply voltage of 1.8 V and most blocks have been designed using a differential architecture. To our knowledge, this is the first log-domain implementation of a front-end for 2-D localization cues extraction. The design has been carried out using a standard double-poly double-metal 0.8 m CMOS process with V _T = 0.8 V. The bandpass filters which form the main core of the chip exhibit a measured dynamic range of 62 dB corresponding to 1.9% THD, while the total power dissipation is 890 W.     

A Very Low Voltage Bipolar Op-Amp for Sensor Applications

A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm², has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported.     

A Low-Voltage Low-Power Rail-to-Rail Constant g m Transconductance Amplifier

In this paper, a low-voltage low-power rail-to-rail constant g _m transconductance amplifier (TA) is introduced. The supply voltages are set at (±1.5 V). The circuit depends on selecting the maximum transconductance (g _m ) to achieve an almost constant g _m over the entire common-mode (CM) range. The circuit is then used to realize a second-order 4 MHz lowpass filter consuming 530 W, and a fifth-order 450 kHz lowpass elliptic filter consuming 2.3 mW. Both filters can be integrated on silicon without any external connections.     

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 W, it has a sufficient input range, whereas conventional Wang's OTA needs 703 W to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.     

一种基于动态阈值NMOS管的1．2V模拟乘法器

基于CSMC0．6μm DPDM CMOS工艺进行设计,利用4个动态闽值NMOS和2个有源电阻实现了一种1．2V低功耗模拟乘法器电路,既节省了输入晶体管数目,又节省了偏置晶体管和偏置电路．1．2V模拟乘法器的输入信号VinA的频率为5MHz,信号峰峰值为1．0V,输入信号VinB的频率为100MHz,信号峰峰值为0．5V时,输出信号Vout的峰峰值为0．35V,一次谐波和三次谐波的差值为40dB．1．2V模拟乘法器输出信号的频带宽度为375MHz,平均电源电流约为30μA,即动态功耗约为36μw,适合于便携式电子产品和带宽要求不太高（400MHz以下）的场合．     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

1.2V低功耗时钟发生器设计

基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。     

低功耗RFID的公钥密码系统实现

安全性是RFID系统继续扩大应用的一个重要障碍。为提高RFID系统的安全性,给出了一种基于公钥密码体制NTRU的实现。并针对RFID标签芯片成本低、计算能力弱、获取能量少的特点,在设计中面向计算时间、小面积和低功耗优化。实现中采用了门控时钟,预计算等措施,使最终电路总计占用2837个等效逻辑门,在时钟频率为500kHz时,电路的功耗为13.68μW。最后给出了与传统密码体系的对比,分析了采取措施的效用。     

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications. Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing. John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents. Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents. Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones. Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems. Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).     

一种6 Gbit/s低功耗低抖动电压模发送器

提出了一种应用于高速串行链路中的基于二阶预加重和阻抗校正技术的6 Gbit/s低功耗低抖动电压模(VM)发送器.在综合分析阻抗、供电电流和输出驱动器预加重等因素影响的基础上,采用了多种技术来提高发送器的信号完整性,主要包括:设计了一种阻抗校正电路(ICU)以保证50 Ω的输出阻抗并抑制信号反射,提出了一种自偏置稳压器用来稳定电源电压,同时设计了一种信号边沿驱动器用以加速信号的转换时间.最终,整个发送器在65 nm CMOS工艺平台进行设计.后仿真结果表明,发送器工作在6 Gbit/s时,远端输出眼图高度大于800 mV,均方根抖动小于2.70 ps.发送器的功耗为16.1 mA,占用面积仅为370 μm×230 μm.     

低频低功耗无源RFID模拟前端设计与分析

介绍了一款低频低功耗无源射频识别(RFID)技术芯片模拟前端的设计.详细介绍了低频RFID模拟前端的整体结构和主要模块.通过对低功耗带隙基准的设计,产生合适的偏置电压,为其他模块提供偏置,以此来限制其他模块的功耗,达到降低整个模拟前端功耗的目的.通过对高性能解调电路的设计,提高解调精度,保证通信过程准确.芯片采用0.35 μm标准CMOS工艺设计和制作,实际测试结果显示,在要求的最远通信距离时,芯片依然可以正常工作,表明该设计满足实际要求.     

0.9V2.4GHz CMOS低噪声放大器设计

使用TSMC0.18μm RF CMOS工艺,设计一个低电压折叠式共源共栅结构低噪声放大器(LNA).利用性能系数FoM(Figure of Merit)衡量其整体性能,并通过仿真找到使FoM最大的偏置电压.使用Cadence SpectreRF仿真表明,在0.9V电源下,2.4GHz处的反射系数良好.噪声系数NF仅为...     

低压CMOS满幅度恒定增益运算放大器设计

运用负反馈控制输入共模电平,实现了电源电压仅为0.9 V的满幅度运算放大器。采用TSMC 0.35μm CMOS工艺参数HSPICE模拟结果显示,在满幅度共模电平下,运放的平均直流电压增益为66.4 dB(10 pF电容负载),增益波动仅为0.01%,平均单位增益带宽为1.88 MHz,平均相位裕度52°,平均静态功耗仅为135μW。     

一种用于A/D转换器的低电压CMOS带隙电压基准源

设计了一种在1V电压下正常工作的用于A/D转换器的低功耗高精度的CMOS带隙电压基准.电路主要包括了一个带隙基准和一个运放电路,而且软启动电路不消耗静态电流.电路采用0.18μm CMOS工艺设计.仿真结果显示,温度从-40~125°C,温度系数约为1.93ppm/°C,同时电源抑制比在10kHz时为38.18dB.电源电压从0.9V到3.4V变化时,输出电压波动保持在0.17%以内;电路消耗总电流为5.18μA.     

Low-Power Constant-Coefficient Multiplier Generator

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) number system, and introducing new simplification techniques and identities, the multiplier features a new algorithm to reduce logic depth for the Wallace-tree implementation. The method also reduces area and complexity.A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications. Synthesis results indicate the new design has smaller area and less power consumption while offering similar speed performance when compared with other multipliers.