Memory LSI reliability

Large-scale integrated (LSI) memory circuit reliability is reviewed. Reliability of large-scale integrated memory circuits is discussed. The major physical mechanisms for failures in memory LSIs and measures to counter these failures are reviewed. Fault-tolerant techniques, divided into the spare row/column line substitution. (SLS) technique and the on-chip error-correcting code (ECC) technique, developed to overcome hard and soft failures are described. Design approaches for realizing high performance and high reliability are also discussed     

LSI reliability prediction based on time

The proposed reliability prediction model takes into account the development of integrated circuit technology as well as the general improvement of the reliability with time.The basic factor of the model is the circuit complexity. Besides the complexity the chip size and temperature factors are also included in the model. The model is applicable to both SSI-, MSI- and LSI-devices.     

纳米工艺提高了LSI铜布线的可靠性

位于日本东京的NEC公司开发出了一种能够在不牺牲布线性能的情况下提高下一代LSI电路中铜布线的可靠性的纳米工艺。该工艺包括两个部分:即在通孔连接界面上插入一层超薄的钛(Ti)薄膜,以及采用氟化碳氮化物(FCN)薄膜来解决长期困扰半导体制造商的一个难题,就是在0.1μm以下的多层布线中出现的可靠性下降。当把钛薄膜加到位于铜布线之间的芯片顶层和底层时,它起胶合剂的作用,可将由应力造成的位移,以及通常与密封装置中的通孔破裂相关联的电迁移减小93%。该工艺通过减小应力和抑制铜迁移的方法在铜通孔处实现了更强的键合。Ti的表面电阻…     

Design considerations leading to the ILLIAC IV LSI process element memories

The authors present the design considerations for a 256-bit bipolar LSI memory component and the system-packaging technology by which the LSI components were assembled to provide seventy 131 072-bit 200-ns full-cycle main process element memories for the ILLIAC IV computing system. The concepts utilized allow memory modularity from about 1024 bytes to over 3,000,000 bytes while maintaining an approximately linear price per bit over the whole range. The experience on LSI memory component and system testing is discussed. Also included are observations on experiences with component designs and prices during the PEM project.     

Some practical considerations for effective and efficient wafer-level reliability control

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions.     

Semicustom and custom LSI technology

Semicustom and custom LSIs have become very important for system manufacturers because they provide system products with distinctive features that cannot be furnished by using only standard LSIs such as microprocessors. From this point of view, rapid development is essential for semicustom and custom LSIs, but there are other factors to be considered for determining the device technology and design methodology such as performance requirements, allowable development costs, and production quantities. In this paper, these aspects for semicustom and custom LSI development are discussed. We first review the device technology and then discuss various design methodologies with an emphasis on standard cell designs. New design methodologies, such as silicon compilers and AI approaches, are also included.     

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems     

Quality assurance system and reliability testing of LSI circuits

The development of LSI circuits as well as their quality and reliability assurance in the current production require, due to the specified high quality levels, a precisely defined Quality Assurance System. Such a System was presented in the first two Sections.For the predictions of field failure rate generally the time-temperature acceleration in accordance with the Arrhenius model has to be applied. Field reliability at lower operating temperatures has to be determined from the results and defectives of sampling life-tests at elevated temperatures. Obviously for LSI circuits the time-temperature acceleration depends very strongly on different failure mechanisms involved. For this reason an efficient and correct failure rate prediction can only be performed, if the failure mechanisms in the defective chips are exactly known and classified.     

Some estimates pertaining to sensitivity and robust stability of input-output systems

The estimates derived in this paper strengthen the available results on sensitivity and robust stability of input-output systems. Two types of estimates are discussed: the “sensitivity type”, which establishes a bound for the output change when the system is perturbed but the input remains the same, and the “robustness type”, which gives a bound for the output change when the input changes but the perturbation does not. First, estimates for general systems over abstract extended spaces are derived; these results are then applied to (1) two frequently used control configurations, and (2) systems governed by vector integral and differential equations on the time domain [0, ∞). The applications of the estimates are illustrated by several examples. This research was supported by the National Science Foundation under Grant #DMS-9102910     

开发LSI DAC新品的技术综述

综述了应用集成运放构成大规模集成电路（LSI）数－模转换器（DAC）的一些关键性技术,并提出了改善DAC性能－价格比的技术措施。     

Polyimide liftoff technology for high-density LSI metallization

A new liftoff technology, in which a metallization layer can be deposited at high temperatures, is developed to provide two-level highly packed interconnection metallization. A heat-resistant polymide, PIQ^®, is employed as the liftoff layer. The reverse pattern of the metallization is formed by reactive sputter etching of the PIQ layer around a thin Mo mask. After metallization layer deposition, lift-off is carried out by electrolytic etching of the Mo mask, thus removing the layer deposited on PIQ. A higher packing density of interlevel connection is also accomplished by adopting exposed via holes. Utilizing this technology, fine-featured smoothly tapered metallization patterns can be obtained almost irrespective of the underlying topology. The minimum pitches of the first level, second level, and via holes are 5, 7, and 7 µm, respectively. This technology does not appear to be detrimental to bipolar device characteristics. A 4096-bit high-speed bipolar memory LSI with two-level highly packed interconnection metallization was produced experimentally utilizing this liftoff technology.     

An inorganic resist technology and its applications to LSI fabrication processes

An Ag/Se-Ge inorganic resist technology is applied to photolithographic processes in LSI fabrication. This paper describes exposure latitude, RIE characteristics, resist fabrication and exposure throughputs, pattern alignment, defocus tolerances and fabrication yields of Al interconnection.Lateral Ag diffusion does not effectively improve the exposure tolerance. The technology exhibits good compatibility with other equipment and technologies, offering satisfactory throughput. Excellent accuracy in pattern alignment is obtained owing to dry-deposition fabrication and the suitable optical properties of the Se-Ge inorganic film, which result in regulated and distinct alignment signals. Defocus tolerance in the resist is larger than that of polymer resist by 2 ∽ 3 μm in the submicron pattern. Al interconnections using this resist demonstrate a short-circuit failure rate of less than 1% and small variation in linewidth having a standard deviation of σ_w = 0.08 μm.In practical processes, the significant advantages of this resist are its bilayer resist structure (doped Ag-Se-Ge and underlying Se-Ge) and its dry deposition, very thin, favorable optical characteristics.     

Laboratory reliability demonstration test considerations

An automotive company's goal is to design and manufacture vehicles that meet the needs and expectations of its customers. Laboratory (lab) testing is a critical step in developing vehicle components or systems. It allows the design engineer to evaluate the design early in the product development process. Establishing a good lab-test minimum-life requirement (bogey) is an important task for the engineer in order to provide a reliable product. When applying the techniques in this paper to the automotive industry, the test procedures can be generalized to any situation for which the Weibull distribution (with known shape parameter) appropriately describes failure behavior, and for which accelerated lab-tests are being correlated with field-test data. This paper covers approaches for determining reliability-test target development, lab-test bogey conversion, and the quantity of test samples (and the test length) which must be tested to meet the reliability demonstration target requirement     

Application of the hierarchical fault model to reliability considerations

The present paper uses the hierarchical fault model. By this it is possible to consider fault propagation in a system based on the layer model. Hardware faults as well as software faults can be described with the same model. Finally, human errors are considered.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

Evaluation of technology options for LSI processing elements

A general overview of the semiconductor technologies available for the manufacture of microprocessor and bit slices is given. Both MOS as well as bipolar processes are covered. Advantages and disadvantages of PMOS, NMOS, CMOS, TTL, ECL, and I²L are discussed. Several of the more special-purpose technologies are briefly mentioned. A comparison is done on the basis of performance, cost, and application, and suggestions are made as to which technology will service best which application. A general prediction is made as to which processes will survive as main stream technologies and what developments can be expected in the near future with respect to improvements. Applications are separated into cost-sensitive low-chip-count areas and high-performance bit-slice-oriented approaches.     

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

A new self-aligning poly-contact technology for MOS LSI

A new self-aligning contact technology suitable for high density MOS LSI is proposed. This technology includes the following steps: 1) coating the polysilicon gate and interconnection areas by the photosensitive resist and baking it into polymalization. With an appropriate viscosity, resist thickness becomes thinner only above the polysilicon areas; and 2) removing selectively the thinned parts of the resist above the polysilicon areas using photo engraved openings of newly coated resist as a mask. This technology is applicable to the conventional Si-gate MOS processes and especially useful for short-channel MOSFET devices because it does not require a high temperature treatment that greatly spreads out the implanted doses compared with the conventional self-aligning contact technology. The high potential of this technology for MOS LSI is verified by the good yield and the high performance of the CMOS PLL (phase-locked-loop) LSI.     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.