Integrated-circuit reliability simulation with emphasis on hot-carrier effects

Reliability assurance and enhancement of analog VLSI circuits are of fundamental importance in the design of high quality signal processing and computing systems. An analog integrated circuit may fial due to degradation of some critical transistors. In this paper, strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. Hot-carrier effects are used to demonstrate the prediction of degradation in circuit performance. This degradation information is propagated through the design hierarchy, with the data at each stage conforming with the complexity of representation at that stage. Circuit topology changes may be made at different levels to reduce the intensive electrical stress applied to weak components. At the top level the chip degradation information is essential for the design of reliable VLSI systems. The method used to include the first-order ac degradation effects into the circuit reliability simulator is described. Experimental results on inverters, precharging circuitry for sense amplifiers, and operational amplifiers designed in submicron technologies are presented.This research was partially supported by National Science Foundation under grant MIP-8710825 and by industrial grants from Samsung Electronics Co. and TRW Inc.     

IC reliability simulation

The motivation and challenges of IC reliability simulation are discussed. The reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot-electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation     

Network reliability with arc failures and repairs

Arc repair probabilities are incorporated into network calculations for directed networks with independent arc failures. A discrete-time Markov chain with one absorbing state is constructed for the problem. The transition probability matrix is used to determine the probability of source-to-sink conductivity in a given time interval, the mean time to source-to-sink connectivity, the fraction of time a node is blocked, and the fraction of time the network is blocked (disconnected). Blockage probabilities aid in repair-crew allocation to the nodes of the network     

A model for system reliability with common-cause failures

A model for the analysis of systems subject to common-cause failures is proposed. The system consists of a finite number of components that are subject to: (1) statistically independent failures, and (2) external failure causes (they need not be mutually statistically independent) for groups of components. Applications to fault-tree analysis and network reliability problems are discussed     

BDD-based reliability analysis of phased-mission systems with multimode failures

This paper proposes a new algorithm (DEP-BDD) based on binary decision diagram (BDD) for reliability analysis of phased-mission systems (PMS) with multimode failures. DEP-BDD is a BDD-based combinatorial model which can be used to deal with more than one kind of dependences by applying dependence algebra, which is a generalization of phase algebra that handles more complex dependences. The nature of the BDD contributes the efficiency and low computational complexity of this algorithm. Two examples are analysed to illustrate the applications and advantages of our approach.     

符合RoHS标准的IC生产的可靠性对业界的挑战

要生产完全环保的符合RoHS标准的产品，对电子行业提出了一系列重大挑战。其中最重要挑战的是要达到更高的焊料处理温度，这一点对集成电路的影响最大。     

Evaluation of system reliability with common-cause failures, by apseudo-environments model

An efficient method for calculating system reliability with CCFs (common-cause failures) is presented by applying the factoring (total probability) theorem when the system and its associated class of CCFs are both arbitrary. Existing methods apply this theorem recursively until no CCF remains to be considered, and so can be time-consuming in computation. The method applies such a theorem only once and can be carried out in two steps: (1) determine each state in terms of the occurrence (or not) of every CCF in the associated class, to regard it as a pseudo-environment and to calculate its probability or weight; (2) determine each resulting subsystem of the system under the environment, calculate its reliability as in the no CCF case and take the weighted sum of such reliabilities, viz, the system reliability. This method is in terms of a Markov process and requires only the occurrence rate of each CCF to obtain the probability of each environment and only the failure rate of each component to obtain the system reliability under each environment; hence, it is practical, efficient, and useful     

A case study of IC storage failures in Taipei trains

Improper storage is one factor than can precipitate failures in electronic products, especially in a hostile environment. In this case study, failures were observed in the propulsion logic modules on trains that were stored in Taiwan for nearly 3 years.Failure analysis was conducted to identify the root cause of IC failures. External inspection showed that contaminants were deposited on the external lead frames. The failure modes in the ceramic packages were observed to be open metallization, although both visual inspection and scanning electron microscopy revealed no trace of corrosion or damage to the die surface. Internal inspection of the plastic dual-in-line packages (P-DIP)s revealed damage to the metallization and glassivation on the die surfaces, and contaminants were found at the failure sites. The major failure mechanism was ionic corrosion, probably caused by high humidity as well as the presence of contaminants in the storage environment or from the device themselves.     

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.     

Modern IC packaging trends and their reliability implications

Reliability aspects are of extreme importance for assembly and packaging, which has become a limiting factor for both cost and performance of electronic systems. On the one hand reliability can be negatively influenced by modern front-end and packaging technology, on the other hand new applications and corresponding field requirements can result in the need for new reliability tests e.g. for mobile devices. Today the three main package trends for mobile devices towards ongoing miniaturization and higher system integration are ball grid array type packages, leadless packages, and wafer level type packages. We present reliability implications based on examples of failures in these modern packaging technologies. We highlight the importance of design for reliability based on results of simulations for a leadless package. For the future it is necessary that test conditions must follow the field requirements to guarantee optimum reliability results.     

Chip warpage model for reliability prediction of delamination failures

A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode.     

ESD: a pervasive reliability concern for IC technologies

Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed     

电阻网络元模拟算法及其在IC设计中的应用

提出了一种模拟任意形状的薄层电阻的方法－－电阻网络元模拟算法。将模拟值和计算值进行比较表明，该方法具有精度高和操作简单的优点，从而在ＩＣ的设计中获得广泛的应用。     

Gate and circuit level analysis of n-type SRAM reliability failures

Gate and circuit level analysis of n-type SRAM failures from experimental time dependent dielectric breakdown (TDDB) testing is presented. Advanced techniques used to successfully isolate and image gate level failure modes include thermally assisted optical emission, parallel polishing, selective polysilicon removal and ultra high resolution (UHR) backscatter electron microscopy. A circuit level failure model founded on confirmed defects is presented which predicts the failure mode distribution. Joule heating is shown to be the primary factor in accelerating defects from formation to catastrophic failure.     

Dependent and multimode failures in reliability evaluation ofextra-stage shuffle-exchange MINs

Previous reliability evaluations for multistage interconnection networks (MINs) assumed that “all failures are statistically-independent and that no degraded operational modes exist for switches”, though these assumptions are not realistic. For example, researchers have described instances of statistically-dependent failures, or fault side-effects, in some MINs. This paper presents efficient algorithms for terminal, broadcast, and K-terminal reliability evaluation of the shuffle-exchange network with an extra stage (SENE), a redundant-path MIN, under assumptions that allow statistical-dependence between failures and degraded operational modes for switches. A modified shock-model incorporates failure statistical-dependency and multiple operational modes into the reliability evaluation. For an N×N SENE, the reliability algorithms and their run-times are: terminal and broadcast →O(log(N)), and K-terminal→O(|K|·log(N))     

A universal reliability prediction model for SMD integrated circuits based on field failures

This paper makes a review of integrated circuit field failures on three types of environment respectively, Ground Benign (G_B), Ground Fixed (G_F), and Airborne Inhabited Cargo (A_IC). It appears that for permanent working G_B, there was no package related failures and 2/3 of the failures had EOS origin. For G_F and A_IC most of the failures were open balls bonds and open solder joints. A universal predicting reliability model is therefore proposed for the die part and for the package part. This study has been carried out in the frame of a working group, to update the French standard UTEC 80810 (ex RDF93 from CNET), and is an alternative guide to the obsolete MIL-HDBK-217F for predicting reliability calculations.     

GOSSIP_DR: A generic software system for IC reliability optimization

In this paper, a generic software system called GOSSIP_DR able to perform Drift Reliability (DR) analysis and optimization is presented. The system was developed based on new drift reliability analysis and optimization methodologies proposed in [1, 2, 3, 4]. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations due to hot electron effects are considered.     

Assembly-level reliability: a methodology for effectivemanufacturing of IC packages

This paper discusses the general methodology of assembly level reliability (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semiconductor packages with assembly-induced defects sometimes do escape detection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimization, but does not guarantee full assembly line balancing for error-free production. ALR is a systematic 4-prong approach which uses a combination of techniques for synergistic effects. (1) Problems of immediate needs have to be addressed and contained, (2) The proper steps must then be taken to ensure that similar issues do not resurface. (3) Design-for-manufacturability principles must be applied; e.g., the design of the package can be simplified to reduce the number of assembly steps, increase throughput, and cut cost. (4) Qualification methodologies have to be revisited. Less expensive but well-characterized test chips can be introduced in lieu of actual devices. Accelerated testing with a good understanding of the failure mechanisms facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, viz, ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts     

Drop impact reliability testing for lead-free and lead-based soldered IC packages

Board-level drop impact testing is a useful way to characterize the drop durability of the different soldered assemblies onto the printed circuit board (PCB). The characterization process is critical to the lead-free (Pb-free) solders that are replacing lead-based (Pb-based) solders. In this study, drop impact solder joint reliability for plastic ball grid array (PBGA), very-thin quad flat no-lead (VQFN) and plastic quad flat pack (PQFP) packages was investigated for Pb-based (62Sn–36Pb–2Ag) and Pb-free (Sn–4Ag–0.5Cu) soldered assemblies onto different PCB surface finishes of OSP (organic solderability preservative) and ENIG (electroless nickel immersion gold). The Pb-free solder joints on ENIG finish revealed weaker drop reliability performance than the OSP finish. The formation of the brittle intermetallic compound (IMC) Cu–Ni–Sn has led to detrimental interfacial fracture of the PBGA solder joints. For both Pb-based and Pb-free solders onto OSP coated copper pad, the formation of Cu₆Sn₅ IMC resulted in different failure sites and modes. The failures migrated to the PCB copper traces and resin layers instead. The VQFN package is the most resistant to drop impact failures due to its small size and weight. The compliant leads of the PQFP are more resistant to drop failures compared to the PBGA solder joints.     

Control of the electromagnetic compatibility: An issue for IC reliability

This paper deals with the use of two main standard modeling approaches in order to control the electromagnetic compatibility of an IC before manufacturing. An application is given in the case of a complex mixed circuit which is an Analog to Digital Converter (ADC) embedded in a microcontroller. The digital core (DC) of the microcontroller consumes dynamic currents which generate internal disturbances and, as a consequence, a loss of the ADC accuracy is observed. At first, the conducted emission of the DC is estimated by using the ICEM-CE model. Then, the ADC immunity is modeled with ICIM-CI methodology. Based on these two models, a simulation at the chip level is performed to estimate the loss of accuracy of this ADC. Finally, this study is the first step in the development of a methodology for virtual prototyping allowing, from the design, the evaluation of the integrated circuit sensitivity to electromagnetic interference in order to improve its reliability.