High‐Performance Flexible Organic Nano‐Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles

Nano‐floating gate memory (NFGM) devices are transistor‐type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe₂O₄) nanoparticles (NPs) as charge trap sites and pentacene as a p‐type semiconductor. Monodisperse CoFe₂O₄ NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle–particle interactions. CoFe₂O₄ NP‐based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I_on/I_off) of ≈2.98 × 10³_, and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe₂O₄ NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high‐performance organic memory devices.     

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Thin insulating layers are used to modulate a depletion region at the source of a thin‐film transistor. Bottom contact, staggered‐electrode indium gallium zinc oxide transistors with a 3 nm Al₂O₃ layer between the semiconductor and Ni source/drain contacts, show behaviors typical of source‐gated transistors (SGTs): low saturation voltage (V_{D_SAT} ≈ 3 V), change in V_{D_SAT} with a gate voltage of only 0.12 V V^?1, and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry: the saturated current changes only 0.15× for 2–50 µm channels and 2× for 9‐45 µm source‐gate overlaps. A higher than expected (5×) increase in drain current for a 30 K change in temperature, similar to Schottky‐contact SGTs, underlines a more complex device operation than previously theorized. Optimization for increasing intrinsic gain and reducing temperature effects is discussed. These devices complete the portfolio of contact‐controlled transistors, comprising devices with Schottky contacts, bulk barrier, or heterojunctions, and now, tunneling insulating layers. The findings should also apply to nanowire transistors, leading to new low‐power, robust design approaches as large‐scale fabrication techniques with sub‐nanometer control mature.     

Organic Ferroelectric‐Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half‐Selection Problem

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF‐TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low‐cost and easy‐fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half‐selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm² V^?1 s^?1 (average) for 2,6‐diphenylanthracene (DPA) and electron mobility of 0.124 cm² V^?1 s^?1 (average) for N ,N ′‐1H,1H‐perfluorobutyl dicyanoperylenecarboxydiimide (PDI‐FCN₂) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric‐based pixelated memory module fabrication.     

Solution‐Processed Wide‐Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field‐Effect Transistor Memory

In this paper, the development of organic field‐effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide‐bandgap (WBG) small‐molecule organic semiconductor material [2‐(9‐(4‐(octyloxy)phenyl)‐9H‐fluoren‐2‐yl)thiophene]3 (WG₃) is reported. The WG₃ NSs are prepared from phase separation by spin‐coating blend solutions of WG₃/trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG₃ film, the device based on WG₃ NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10⁴ s), and reliable switching properties. A quantitative study of the WG₃ NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge‐exciton annihilation efficiency induced by increased contact area between the WG₃ NSs and pentacene layer. This versatile solution‐processing approach to preparing WG₃ NSs arrays as charge trapping sites allows for fabrication of high‐performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials.     

SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

The minimization of the subthreshold swing (SS) in transistors is essential for low‐voltage operation and lower power consumption, both critical for mobile devices and internet of things (IoT) devices. The conventional metal‐oxide‐semiconductor field‐effect transistor requires sophisticated dielectric engineering to achieve nearly ideal SS (60 mV dec^?1 at room temperature). However, another type of transistor, the junction field‐effect transistor (JFET) is free of dielectric layer and can reach the theoretical SS limit without complicated dielectric engineering. The construction of a 2D SnSe/MoS₂ van der Waals (vdW) heterostructure‐based JFET with nearly ideal SS is reported. It is shown that the SnSe/MoS₂ vdW heterostructure exhibits excellent p–n diode rectifying characteristics with low saturate current. Using the SnSe as the gate and MoS₂ as the channel, the SnSe/MoS₂ vdW heterostructure exhibit well‐behavioured n‐channel JFET characteristics with a small pinch‐off voltage V_P of ?0.25 V, nearly ideal subthreshold swing SS of 60.3 mV dec^?1 and high ON/OFF ratio over 10⁶, demonstrating excellent electronic performance especially in the subthreshold regime.     

Graphene–Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating‐gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH₃⁺), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al₂O₃ blocking dielectric layers. Important design rules are proposed for a high‐performance graphene memory device: i) precise doping of the graphene channel, and ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor‐type memory device. Additionally, the positively charged GO (GO–NH₃⁺) interacts electrostatically with hydroxyl groups of both UV‐treated Al₂O₃ and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene–graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10⁵ s), and good mechanical stability (1000 cycles).     

A High‐Performance Top‐Gated Graphene Field‐Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric

A high‐performance top‐gated graphene field‐effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface‐energy‐engineered copolymer gate dielectric via a solvent‐free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane and 1‐vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p‐doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (V_Dirac) of the graphene FET can thus be systematically controlled. In particular, the V_Dirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field‐effect hole and electron mobility values of over 7200 and 3800 cm² V^?1 s^?1, respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high‐frequency flexible device applications.     

Non‐Volatile ReRAM Devices Based on Self‐Assembled Multilayers of Modified Graphene Oxide 2D Nanosheets

2D nanomaterials have been actively utilized in non‐volatile resistive switching random access memory (ReRAM) devices due to their high flexibility, 3D‐stacking capability, simple structure, transparency, easy fabrication, and low cost. Herein, it demonstrates re‐writable, bistable, transparent, and flexible solution‐processed crossbar ReRAM devices utilizing graphene oxide (GO) based multilayers as active dielectric layers. The devices employ single‐ or multi‐component‐based multilayers composed of positively charged GO (N‐GO(+) or NS‐GO(+)) with/without negatively charged GO(‐) using layer‐by‐layer assembly method, sandwiched between Al bottom and Au top electrodes. The device based on the multi‐component active layer Au/[N‐GO(+)/GO(‐)]_n/Al/PES shows higher ON/OFF ratio of ≈10⁵ with switching voltage of ?1.9 V and higher retention stability (≈10⁴ s), whereas the device based on single component (Au/[N‐GO(+)]_n/Al/PES) shows ≈10³ ON/OFF ratio at ±3.5 V switching voltage. The superior ReRAM properties of the multi‐component‐based device are attributed to a higher coating surface roughness. The Au/[N‐GO(+)/GO(–)]_n/Al/PES device prepared from lower GO concentration (0.01%) exhibits higher ON/OFF ratio (≈10⁹) at switching voltage of ±2.0 V. However, better stability is achieved by increasing the concentration from 0.01% to 0.05% of all GO‐based solutions. It is found that the devices containing MnO₂ in the dielectric layer do not improve the ReRAM performance.     

Polymer Doping Enables a Two‐Dimensional Electron Gas for High‐Performance Homojunction Oxide Thin‐Film Transistors

High‐performance solution‐processed metal oxide (MO) thin‐film transistors (TFTs) are realized by fabricating a homojunction of indium oxide (In₂O₃) and polyethylenimine (PEI)‐doped In₂O₃ (In₂O₃:x% PEI, x = 0.5–4.0 wt%) as the channel layer. A two‐dimensional electron gas (2DEG) is thereby achieved by creating a band offset between the In₂O₃ and PEI‐In₂O₃ via work function tuning of the In₂O₃:x% PEI, from 4.00 to 3.62 eV as the PEI content is increased from 0.0 (pristine In₂O₃) to 4.0 wt%, respectively. The resulting devices achieve electron mobilities greater than 10 cm² V^?1 s^?1 on a 300 nm SiO₂ gate dielectric. Importantly, these metrics exceed those of the devices composed of the pristine In₂O₃ materials, which achieve a maximum mobility of ≈4 cm² V^?1 s^?1. Furthermore, a mobility as high as 30 cm² V^?1 s^?1 is achieved on a high‐k ZrO₂ dielectric in the homojunction devices. This is the first demonstration of 2DEG‐based homojunction oxide TFTs via band offset achieved by simple polymer doping of the same MO material.     

Low Schottky Barrier Black Phosphorus Field‐Effect Devices with Ferromagnetic Tunnel Contacts

Black phosphorus (BP) has been recently unveiled as a promising 2D direct bandgap semiconducting material. Here, ambipolar field‐effect transistor behavior of nanolayers of BP with ferromagnetic tunnel contacts is reported. Using TiO₂/Co contacts, a reduced Schottky barrier <50 meV, which can be tuned further by the gate voltage, is obtained. Eminently, a good transistor performance is achieved in the devices discussed here, with drain current modulation of four to six orders of magnitude and a mobility of μ_h ≈ 155 cm² V^?1 s^?1 for hole conduction at room temperature. Magnetoresistance calculations using a spin diffusion model reveal that the source–drain contact resistances in the BP device can be tuned by gate voltage to an optimal range for injection and detection of spin‐polarized holes. The results of the study demonstrate the prospect of BP nanolayers for efficient nanoelectronic and spintronic devices.     

An organic nonvolatile memory using space charge polarization of a gate dielectric

We realize a nonvolatile and rewritable memory effect in an organic field-effect transistor (OFET) structure using polymethylmethacryrate (PMMA) dispersed with 10-methyl-9-phenylacridinium perchlorate (MPA⁺ClO₄⁻) as a gate dielectric. Applying a voltage between a top source-drain electrode and a bottom gate electrode induces electrophoresis of two ions of MPA⁺ and ClO₄⁻ towards the corresponding electrodes in the memory devices. The drain currents of the memory devices markedly increase from 10^− 9 A to 10^− 2 A under no gate voltage condition due to the strong space charge polarization effect. Our memory devices have excellent electrical bistability and retention characteristics, i.e. the memory on/off ratio reached 10⁷ and the drain current maintained 40% of the initial value after 10⁴ s.     

Charge‐Storage Aromatic Amino Compounds for Nonvolatile Organic Transistor Memory Devices

Here, charge‐storage nonvolatile organic field‐effect transistor (OFET) memory devices based on interfacial self‐assembled molecules are proposed. The functional molecules contain various aromatic amino moieties (N‐phenyl‐N‐pyridyl amino‐ (PyPN), N‐phenyl amino‐ (PN), and N,N‐diphenyl amino‐ (DPN)) which are linked by a propyl chain to a triethoxysilyl anchor group and act as the interface modifiers and the charge‐storage elements. The PyPN‐containing pentacene‐based memory device (denoted as PyPN device) presents the memory window of 48.43 V, while PN and DPN devices show the memory windows of 24.88 and 8.34 V, respectively. The memory characteristic of the PyPN device can remain stable along with 150 continuous write‐read‐erase‐read cycles. The morphology analysis confirms that three interfacial layers show aggregation due to the N atomic self‐catalysis and hydrogen bonding effects. The large aggregate‐covered PyPN layer has the full contact area with the pentacene molecules, leading to the high memory performance. In addition, the energy level matching between PyPN molecules and pentacene creates the smallest tunneling barrier and facilitates the injection of the hole carriers from pentacene to the PyPN layer. The experimental memory characteristics are well in agreement with the computational calculation.     

A Centimeter‐Scale Inorganic Nanoparticle Superlattice Monolayer with Non‐Close‐Packing and its High Performance in Memory Devices

Due to the near‐field coupling effect, non‐close‐packed nanoparticle (NP) assemblies with tunable interparticle distance (d) attract great attention and show huge potential applications in various functional devices, e.g., organic nano‐floating‐gate memory (NFGM) devices. Unfortunately, the fabrication of device‐scale non‐close‐packed 2D NPs material still remains a challenge, limiting its practical applications. Here, a facile yet robust “rapid liquid–liquid interface assembly” strategy is reported to generate a non‐close‐packed AuNP superlattice monolayer (SM) on a centimeter scale for high‐performance pentacene‐based NFGM. The d and hence the surface plasmon resonance spectra of SM can be tailored by adjusting the molecular weight of tethered polymers. Precise control over the d value allows the successful fabrication of photosensitive NFGM devices with highly tunable performances from short‐term memory to nonvolatile data storage. The best performing nonvolatile memory device shows remarkable 8‐level (3‐bit) storage and a memory ratio over 10⁵ even after 10 years compared with traditional devices with a AuNP amorphous monolayer. This work provides a new opportunity to obtain large area 2D NPs materials with non‐close‐packed structure, which is significantly meaningful to microelectronic, photovoltaics devices, and biochemical sensors.     

Printing Semiconductor–Insulator Polymer Bilayers for High‐Performance Coplanar Field‐Effect Transistors

Source–semiconductor–drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next‐generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross‐talk among different devices, and simplify the fabrication process of circuits. Here, a one‐step, drop‐casting‐like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3‐hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO₂ dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor–insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor–insulator bilayer structure is an ideal system for injecting charges into the insulator via gate‐stress, and the thus‐formed PS electret layer acts as a “nonuniform floating gate” to tune the threshold voltage and effective mobility of the transistors. Effective field‐effect mobility higher than 1 cm² V^?1 s^?1 with an on/off ratio > 10⁷ is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits.     

Inorganic Nano Light‐Emitting Transistor: p‐Type Porous Silicon Nanowire/n‐Type ZnO Nanofilm

An inorganic nano light‐emitting transistor (INLET) consisting of p‐type porous Si nanowires (PoSiNWs) and an n‐type ZnO nanofilm was integrated on a heavily doped p‐type Si substrate with a thermally grown SiO₂ layer. To verify that modulation of the Fermi level of the PoSiNWs is key for switchable light emitting, I–V and electroluminescent characteristics of the INLET are investigated as a function of gate bias (V _g). As the V _g is changed from 0 V to ?20 V, the current level and light‐emission intensity in the orange–red range increase by three and two times, respectively, with a forward bias of 20 V in the p–n junction, compared to those at a V _g of 0 V. On the other hand, as the V _g approaches 10 V, the current level decreases and the emission intensity is reduced and then finally switched off. This result arises from the modulation of the Fermi level of the PoSiNWs and the built‐in potential at the p–n junction by the applied gate electric field.     

Roll‐to‐Roll Production of Layer‐Controlled Molybdenum Disulfide: A Platform for 2D Semiconductor‐Based Industrial Applications

A facile methodology for the large‐scale production of layer‐controlled MoS₂ layers on an inexpensive substrate involving a simple coating of single source precursor with subsequent roll‐to‐roll‐based thermal decomposition is developed. The resulting 50 cm long MoS₂ layers synthesized on Ni foils possess excellent long‐range uniformity and optimum stoichiometry. Moreover, this methodology is promising because it enables simple control of the number of MoS₂ layers by simply adjusting the concentration of (NH₄)₂MoS₄. Additionally, the capability of the MoS₂ for practical applications in electronic/optoelectronic devices and catalysts for hydrogen evolution reaction is verified. The MoS₂‐based field effect transistors exhibit unipolar n‐channel transistor behavior with electron mobility of 0.6 cm² V^?1 s^?1 and an on‐off ratio of ≈10³. The MoS₂‐based visible‐light photodetectors are fabricated in order to evaluate their photoelectrical properties, obtaining an 100% yield for active devices with significant photocurrents and extracted photoresponsivity of ≈22 mA W^?1. Moreover, the MoS₂ layers on Ni foils exhibit applicable catalytic activity with observed overpotential of ≈165 mV and a Tafel slope of 133 mV dec^?1. Based on these results, it is envisaged that the cost‐effective methodology will trigger actual industrial applications, as well as novel research related to 2D semiconductor‐based multifaceted applications.     

Flexible Nonvolatile Transistor Memory with Solution‐Processed Transition Metal Dichalcogenides

Nonvolatile field‐effect transistor (FET) memories containing transition metal dichalcogenide (TMD) nanosheets have been recently developed with great interest by utilizing some of the intriguing photoelectronic properties of TMDs. The TMD nanosheets are, however, employed as semiconducting channels in most of the memories, and only a few works address their function as floating gates. Here, a floating‐gate organic‐FET memory with an all‐in‐one floating‐gate/tunneling layer of the solution‐processed TMD nanosheets is demonstrated. Molybdenum disulfide (MoS₂) is efficiently liquid‐exfoliated by amine‐terminated polystyrene with a controlled amount of MoS₂ nanosheets in an all‐in‐one floating‐gate/tunneling layer, allowing for systematic investigation of concentration‐dependent charge‐trapping and detrapping properties of MoS₂ nanosheets. At an optimized condition, the nonvolatile memory exhibits memory performances with an ON/OFF ratio greater than 10⁴, a program/erase endurance cycle over 400 times, and data retention longer than 7 × 10³ s. All‐in‐one floating‐gate/tunneling layers containing molybdenum diselenide and tungsten disulfide are also developed. Furthermore, a mechanically‐flexible TMD memory on a plastic substrate shows a performance comparable with that on a hard substrate, and the memory properties are rarely altered after outer‐bending events over 500 times at the bending radius of 4.0 mm.     

An All‐Solution‐Based Hybrid CMOS‐Like Quantum Dot/Carbon Nanotube Inverter

The development of low‐cost, flexible electronic devices is subordinated to the advancement in solution‐based and low‐temperature‐processable semiconducting materials, such as colloidal quantum dots (QDs) and single‐walled carbon nanotubes (SWCNTs). Here, excellent compatibility of QDs and SWCNTs as a complementary pair of semiconducting materials for fabrication of high‐performance complementary metal‐oxide‐semiconductor (CMOS)‐like inverters is demonstrated. The n‐type field effect transistors (FETs) based on I^? capped PbS QDs (V _th = 0.2 V, on/off = 10⁵, S _S‐th = 114 mV dec^?1, µ _e = 0.22 cm² V^?1 s^?1) and the p‐type FETs with tailored parameters based on low‐density random network of SWCNTs (V _th = ?0.2 V, on/off > 10⁵, S _S‐th = 63 mV dec^?1, µ _h = 0.04 cm² V^?1 s^?1) are integrated on the same substrate in order to obtain high‐performance hybrid inverters. The inverters operate in the sub‐1 V range (0.9 V) and have high gain (76 V/V), large maximum‐equal‐criteria noise margins (80%), and peak power consumption of 3 nW, in combination with low hysteresis (10 mV).     

A High‐Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3‐d;2′,3′‐d′]naphtho[2,3‐b;6,7‐b′]dithiophene (BBTNDT) organic field‐effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm² V^?1 s^?1, photoresponsivity of 433 A W^?1, and long retention time for more than 6 h with a current ratio larger than 10⁶. Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2‐b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high‐performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer.     

Negative Transconductance Heterojunction Organic Transistors and their Application to Full‐Swing Ternary Circuits

Multivalued logic (MVL) computing could provide bit density beyond that of Boolean logic. Unlike conventional transistors, heterojunction transistors (H‐TRs) exhibit negative transconductance (NTC) regions. Using the NTC characteristics of H‐TRs, ternary inverters have recently been demonstrated. However, they have shown incomplete inverter characteristics; the output voltage (V_OUT) does not fully swing from V_DD to G_ND. A new H‐TR device structure that consists of a dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene (DNTT) layer stacked on a PTCDI‐C13 layer is presented. Due to the continuous DNTT layer from source to drain, the proposed device exhibits novel switching behavior: p‐type off/p‐type subthreshold region /NTC/ p‐type on. As a result, it has a very high on/off current ratio (≈10⁵) and exhibits NTC behavior. It is also demonstrated that an array of 36 of these H‐TRs have 100% yield, a uniform on/off current ratio, and uniform NTC characteristics. Furthermore, the proposed ternary inverter exhibits full V_DD‐to‐G_ND swing of V_OUT with three distinct logic states. The proposed transistors and inverters exhibit hysteresis‐free operation due to the use of a hydrophobic gate dielectric and encapsulating layers. Based on this, the transient operation of a ternary inverter circuit is demonstrated for the first time.