A 622-Mb/s 8×8 ATM switch chip set with shared multibufferarchitecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8-μm BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8×8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing     

ADSP-TS201的系统设计及外部总线接口技术

主要介绍ADI公司的新一代高性能数字信号处理芯片ADSP-TS201(AD9103XX系列)的内部结构和性能。着重讨论了TS201的系统设计及在设计过程中需要特别注意的问题,并根据TS201自身的结构特点,结合FPGA,SDRAM的接口实例讨论了TS201的外部总线接口技术,并可作为该系列DSP的应用系统设计的参考。     

Interface LSIs for data terminals and facsimile

Describes three high-performance interface LSIs, namely, the facsimile modem, universal receiver transmitter, and code converter LSIs, for facsimile, for communication control equipment, and for a digital service unit to connect the terminal equipment and the network. It is explained that optimization in block partitioning and common use of building block cells has been chosen as the LSI design method. These LSIs operate at from 1.4 (facsimile modem) to 6.1 MHz (universal transmitter receiver) clock frequencies with an adequate operating frequency margin. The power dissipation is 450-500 mW at 5 V the power supply voltage. The chip size for these LSIs is from 39 to 44 mm/SUP 2/. The LSIs consist of about 20000 transistors each. The output level is TTL compatible.     

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era

“More than Moore” is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach—SiP or SoC—before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.      

VLSI in picture coding

Recent LSI technology development for motion video coding is described briefly. The standard coding algorithms discussed recently are based on interframe coding with motion compensation and DCT (Discrete Cosine Transform). LSIs for realizing the signal processing functions are shown as functions of integration scale and chip area. Custom design LSI chips for the interframe encoder and decoder, meeting the H.261 and MPEG standards, are shown. Also, progress of programmable video signal processors (VSP) are overviewed.     

Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

VLSI in picture coding

Recent LSI technology development for motion video coding is described briefly. The standard coding algorithms discussed recently are based on interframe coding with motion compensation and DCT (Discrete Cosine Transform). LSIs for realizing the signal processing functions are shown as functions of integration scale and chip area. Custom design LSI chips for the interframe encoder and decoder, meeting the H.261 and MPEG standards, are shown. Also, progress of programmable video signal processors (VSP) are overviewed.     

基于FPGA的数字中频信号处理平台的设计与实现

随着通信系统对信号处理的要求不断提高,传统芯片难以满足高速处理的要求。 FPGA 以并行处理能力强、集成度高、可系统重构等特点得到了广泛应用。本文设计了以高性能 FPGA 为核心,具有嵌入式 ARM 的 SOC 功能,结合 CPLD、DSP、ADC 等技术,组合 SDRAM、 FLSAH 存储器等外围电路构建一款中频数字信号处理和数据处理平台。经工程实践验证,系统设计可靠、运行稳定。     

基于FPGA的简易数字存储示波器设计

主要以简易数字存储示波器为例,介绍可编程逻辑器件在模数转换、数模转换及数据存储与处理中的设计方法。此系统由四部分组成,其中数据处理及存储单元用VHDL语言进行设计,利用MAX＋PLUSII软件进行电路仿真,并选用FP6A硬件实现;输入单元及输出单元采用AD976及AD669芯片实现;存储器RAM采用HM6264芯片实现。设计中采用了白顶向下的方法,将系统按逻辑功能划分模块,各模块使用VHDL语言进行设计,在ISE中完成软件的设计和仿真。     

基于FPGA的微光视频采集与预处理系统设计

针对当前微光视频图像采集与处理系统中数据处理量与系统实时性之间的矛盾,设计了一种基于现场可编程门阵列(Field Programmable Gate Array, FPGA)的实时信号采集与预处理系统。该系统以高性能Xilinx A7系列芯片为主控芯片,使用两片第二代双倍数据率同步动态随机存取存储器(Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM)作为核心存储器件,并定制超感光互补金属氧化物半导体(Complementary Metal Oxide Semiconductor, CMOS)传感镜头作为视频图像采集器件。完成系统的硬件设计之后,通过Xilinx Vivado平台以及Matlab进行软件系统的工程设计与仿真分析,实现了微光环境下视频图像的采集、存储、处理与显示的全过程。实验结果表明,该系统采集的微光视频图像实时性好、动态画面流畅。     

Semicustom and custom LSI technology

Semicustom and custom LSIs have become very important for system manufacturers because they provide system products with distinctive features that cannot be furnished by using only standard LSIs such as microprocessors. From this point of view, rapid development is essential for semicustom and custom LSIs, but there are other factors to be considered for determining the device technology and design methodology such as performance requirements, allowable development costs, and production quantities. In this paper, these aspects for semicustom and custom LSI development are discussed. We first review the device technology and then discuss various design methodologies with an emphasis on standard cell designs. New design methodologies, such as silicon compilers and AI approaches, are also included.     

1.5 μm CMOS gate arrays with analog/digital macros designedusing common base arrays

Mixed analog and digital circuits are realized on a 1.5 μm silicon-gate CMOS chip with +5 V power supply only. The circuit uses CMOS digital gate arrays of 0.32 K to 19.6 K cells and is created without any additional turnaround time or any restriction on the design. Typical internal digital gate (two-input NAND) speed, with a fanout of 3 and a wire length of 3 mm, is 1.4 ns. A voltage comparator with ±8 mV maximum input offset voltage and 60 ns response time, digital-to-analog and analog-to-digital converters with 4-, 6-, and 8-bit resolution, respectively, and an analog switch of 25 Ω on-resistance can be realized on the same chip with digital circuits. Using this technology, about one-tenth of the turnaround time can be achieved compared with full-custom LSIs for the same system. The product development flow and computer-aided-design tools for designing mixed analog and digital gate arrays are the same as for digital gate arrays     

Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system

Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.<>     

基于Nios II软核的运动目标检测系统设计

介绍了一种基于Nios II的运动视频检测片上系统,该系统通过采用软/硬件协同设计的方法,使用Altera EP2C35 FPGA芯片与HV7131R视频摄像头配合实现了高速的数字视频处理,选用SDRAM和FLASH作为视频数据的外部存储器,满足了运动检测和保存运动现场的需要.并且采用Verilog HDL和Nios II定制指令使用硬件实现了系统的大部分功能,提高系统的处理速度,同时具有良好的灵活性和适应性.     

基于ADSP-TS201S的双片DSP处理器并行工作的软件实现

介绍了一种基于ADI公司的双片ADSP-TS201S型DSP芯片的数字信号处理器并行工作模式的设计。采用EPROM加载和链路口加载的方式分别对主片和从片进行程序的引导加载。简单介绍两片DSP的分工工作模式:其中主片DSP可以用于与外部进行数据交互通信和对双片DSP的控制管理;从片DSP可以专用于整个系统核心算法的实现。两片DSP通过DMA中断进行算法的同步以保证整个系统的实时运转。大致介绍系统构成,远程管控的实现方式。详细介绍主片的远程参数数据库和核心算法程序的更新所采用的设计方法。主片接收外部传递的信息及数据采用中断模式进行。     

基于ADSP-TS201S的数字信号处理器设计

简要介绍DSP芯片ADSP-TS201S的结构和性能以及它的特点,并以此为基础简述利用ADSP-TS201S构成多DSP并行处理系统的原理和方法,且给出一种模块化的双通道(和/差两路)数字信号处理平台的原理框图.     

Post-fabrication clock-timing adjustment using genetic algorithms

To solve the problem of fluctuations in clock timing (also known as "clock skew" problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GAs). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: 1) enhancement in clock frequencies leading to improved operational yields; 2) lower power supply voltages, while maintaining operational yield; and 3) reductions in design times. Two different LSIs have been developed: the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time.     

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A 256-element associative parallel processor

A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system     

基于TS201平台的雷达信号处理机设计

以ADI公司高性能浮点DSP芯片TS201为核心处理器,结合Xilinx公司VIRTEX-IIPRO系列FPGA芯片设计的2片DSP数据缓存板和4片DSP主处理板,设计了一种雷达信号处理机。该信号处理机中,DSP芯片仅用链路口完成相互间点对点的通信,各自的数据总线互补相连,存储器空间地址彼此独立。系统具有硬件结构体积小,程序易调试,整体可靠性高的优点。