RF模型综述

文章主要讨论了RF模型的现状和应用前景。首先说明了RF模型的一般要求，然后对其中的核心问题和目前关注的焦点进行了分析，如寄生元件尤其是栅电阻和衬底电阻网络的建模、非准静态效应的建模和高频噪声的建模等。同时，还简单介绍了目前通用的简单模型。最后，提出了改进RF模型的方向和策略。     

多晶硅TFT模型的研究进展

全面介绍了多晶硅薄膜晶体管(TFT)紧凑模型的现状和应用前景,简单说明了多晶硅TFT特有的电学特性,这是多晶硅TFT建模的基础,重点介绍了基于阈值电压和基于表面势的多晶硅TFT紧凑模型的研究进展,并对这些模型进行了评述,其中RPI模型是基于阈值电压的TFT模型的典范.虽然TFT模型已经有所发展,但成熟度还远远不够.最后提出了改进多晶硅TFT模型的方向和策略,包括二维器件模拟的应用、基于表面势模型的发展、多晶硅材料特性的应用、统一模型的发展、短沟效应的建模和参数提取等.     

HiSIM2 Circuit simulation - Solving the speed versus accuracy crisis

The development trend in compact modeling goes toward surface-potential-based approaches and leads to models like HiSIM2, with higher accuracy, fewer model parameters, and shorter computer runtime than achievable with the conventional threshold-voltage-based approaches. The main motivation for continuing this development effort is to realize a sufficient design capability of RF circuits with advanced MOSFETs, where many higher-order phenomena affect the circuit performance, as well as of large mixed-signal circuits, where both accuracy and short simulation time are a must. The trend toward the surface potential brings compact modeling for circuit simulation also much closer to 2D and three-dimensional numerical device simulation. Therefore, both approaches can now come together and work united to achieve the common goal of realizing rapid technology progress for the benefit of the society     

Microwave FinFET modeling based on artificial neural networks including lossy silicon substrate

Nowadays, FinFET represents a new and promising transistor structure for the aggressive downscaling of the CMOS technology. Typically, the small-signal modeling for FinFET is based on compact models or on equivalent circuit representations. As an alternative to such approaches, a small-signal behavioral model based on artificial neural networks is developed in this paper. Particular attention is devoted to modeling the low-frequency kinks of the scattering parameters, due to the lossy silicon substrate. The model is efficient and accurate, as confirmed by the comparison between measured and simulated microwave behavior.     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.     

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.     

Black box modelling of the Op-Amp including switching power supply on effect

In general, models at the device and circuit levels are very important in system design. Building compact models at the circuit level is complicated, needs a lot of physical information about the circuit and moreover it has a long simulation time. We present in this paper an alternative modeling methodology, black box modeling. In this technique, we need only the output behavior of the circuit. We get this behavior either from measurements or simulations from previously built compact models. We apply this technique to the operational amplifier as a case study. We use the Op-Amp, BSIM3v3-based compact transistor model, to obtain the performance of the circuit. An excellent agreement is obtained between the output voltage from the black box model of the Op-Amp (for both of the effect of the switching power supply on and the steady state behavior) and the corresponding output from the model used to build it.     

High-speed interconnects with underlayer orthogonal metal grids

On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of conventional microstrip lines. The dispersion reduction comes from suppressing higher order modes; the local speed of light reduction comes from a longer current return path. These characteristics are beneficial for compact CMOS analog circuit designs. Losses caused by substrate and conductor lines are restrained by shielding the substrate and by involving weaker electric fields. Resonance at a frequency characterized by that of a patch antenna was observed and needs to be considered in high-speed circuit designs. The grids have weaker effects in the case of CPWs, where the side ground plate effects are significant. A signal transmission example shows that dispersion and frequency-dependent losses are important in determining the signal rise edge. Semi-empirical distributed resistance-inductance-capacitance-conductance (RLCG) equivalent circuit models are constructed for the interconnects below the resonant frequencies.     

Influence of quasi-ballistic base transport on the small signaly-parameters of Si bipolar transistors

The small-signal forward y-parameters of a Si bipolar transistor are evaluated from a 1-flux solution to the Boltzmann transport equation. For base widths less than 0.1 μm, results begin to deviate significantly from those predicted by the conventional diffusion analysis. In particular, the phase of the y-parameter, an important factor in analog circuit design, is shown to be especially sensitive to quasi-ballistic transport. Compact circuit models will become increasingly inaccurate as base widths continue to shrink. The approach used here eliminates the restriction to a long base and can serve as the basis for improved compact circuit modeling     

Organic Thin-Film Transistors: Part I—Compact DC Modeling

A generic analytical model for the current–voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation—linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current–voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.      

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm² cross-sectional area     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

A monolithic low power PCM repeater circuit

Describes a monolithic regenerative repeater circuit for T-1 type PCM transmission systems. The bipolar IC chip contains all the functional blocks and active components required for the regenerative repeater system, including the automatic line build out (ALBO) circuitry. It offers significant performance, power reduction, and reliability advantages over conventional PCM repeater designs. Discusses the design approach and the system architecture of the monolithic repeater chip, and demonstrates some of the key performance features.     

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.     

一种紧凑的GaN高电子迁移率晶体管大信号模型拓扑

GaN高电子迁移率晶体管（HEMT）以其复杂的器件特性使其大信号建模变得十分困难,尽管EEHEMT、Angelov等模型结构曾经成功应用于GaAs HEMT/MESFET的大信号模型,但当它们被用于GaN HEMT建模时却不再准确和完备.面向GaN HEMT器件的大信号模型,本文提出了一种紧凑的模型拓扑,此模型拓扑综合了GaN HEMT器件的直流电压-电流（I-V）特性、非线性电容、寄生参数、栅延迟漏延迟与电流崩塌、自热效应以及噪声等特性.经验证此模型拓扑在仿真中具有很好的收敛性,适用于GaN HEMT器件的大信号模型的建立,满足GaN基微波电路设计对器件模型的需求.     

Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

Impact of Scaling on Analog Performance and Associated Modeling Needs

This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to evaluate the impact of nonminimum gate length and alternate doping profiles. Results indicate that the modeling of moderate-to-weak inversion behavior will continue to grow in importance. Simulations suggest that using nonminimum length and drain-side engineered devices at the 45-nm technology node offers an attractive degree of freedom for analog circuit design.     

MOSFET集约模型的发展

MOSFET集约模型作为连接半导体生产商与电路设计者之间的桥梁,是半导体行业不可或缺的一环。随着对器件物理效应的不断深入了解,以及不断满足电路设计新要求,MOSFET集约模型经历了长时间的发展。从模型的基础出发,介绍了基于阈值电压Vth、反型层电荷Qi和表面势Φs这三类MOSFET集约模型的发展历程及其主要特征。     

Practical modeling for circuit simulation

There is much more to modeling for circuit simulation than deriving a set of I(V), and perhaps Q(V), equations and extracting a SPICE MODEL card. Unfortunately, some practical aspects of modeling are often overlooked. This paper details common-sense guidelines for modeling and highlights common modeling problems. Particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk