InAs/GaSb Ⅱ类超晶格长波红外探测器的表面处理研究

开展了In As/Ga Sb Ⅱ类超晶格长波红外探测器的表面处理研究。通过对不同处理工艺形成台面器件的暗电流分析,发现N₂O等离子处理结合快速热退火(RTA)的优化工艺能够显著改善长波器件电学性能。对于50%截止波长12.3μm的长波器件,在液氮温度,-0.05 V偏置下,表面处理后暗电流密度从5.88×10^-1 A/cm²降低至4.09×10^-2 A/cm²,零偏下表面电阻率从17.7Ωcm提高至284.4Ωcm,有效降低侧壁漏电流。但是该表面处理后的器件在大反偏压下仍有较大的侧壁漏电,这可能是由于高浓度的表面电荷使得大反偏下侧壁存在较高的隧穿电流。通过栅控结构器件的变栅压实验,验证了长波器件存在纯并联电阻及表面隧穿两种主要漏电机制。最后,对表面处理前后的暗电流进行拟合,处理后器件表面电荷浓度为3.72×10¹¹ cm^-2。     

水基溶液法IGZO-TFT的电学特性研究

采用水基溶液法制备铟镓锌氧化物薄膜晶体管(IGZO-TFT),研究了在有无紫外光辅助退火条件下,不同后退火温度(270,300,330,360和400℃)对IGZO-TFT器件电学性能的影响。研究发现,IGZO-TFT在后退火温度为360℃时器件电学性能最佳,从而证明了水基溶液法在小于400℃的低温下可以制备IGZO-TFT。同时,研究表明,在后退火温度为360℃时,与无紫外光辅助退火IGZO-TFT相比,经紫外光辅助退火IGZO-TFT的饱和迁移率从1.19 cm²/Vs增加到1.62 cm²/Vs,正栅偏压偏移量从8.7 V降低至4.6 V,负栅偏压偏移量从-9.7 V降低至-4.4 V,从而证明了紫外光辅助退火对IGZO薄膜具有激活与钝化作用,可以优化IGZO-TFT器件的电学性能。     

退火处理对ITO表面特性及有机发光器件性能的影响

为了改善有机发光器件（OLEDs）的性能，在0～600℃不同温度下对ITO透明导电玻璃进行了退火处理。SEM观察到随退火温度的升高，ITO表面粗糙度增加；四探针电阻测试结果显示，在300℃以上温度退火后ITO表面电阻率有明显增加。用退火前后的ITO玻璃作为阳极制备了OLEDs，器件结构为ITO／TPD／Alq3／Al，比较器件的电流密度-电压特性曲线测试结果表明，ITO薄膜的热处理温度对OLEDs性能有显著的影响。     

超临界流体改善IGZO薄膜晶体管光电特性研究

随着高速、高分辨率、全透明的显示技术不断发展，对全透明薄膜晶体管(Thin-Film Transistor, TFT)的电学和光学性能均提出了更高的要求。首先在玻璃衬底上制备了以非晶铟镓锌氧化物(Amorphous Indium-Gallium-Zinc Oxide, a-IGZO)为有源层、铟锡氧化物(Indium Tin Oxide, ITO)为电极的全透明薄膜晶体管。并以低温环保的超临界流体技术进一步改善器件特性，超临界流体具有高溶解和高渗透性，可进入器件内部，修复材料中的断键，消除器件的缺陷，进而提升器件综合性能。实验结果表明，处理后器件的亚阈值摆幅从451.44 mV/dec下降至231.56 mV/dec,载流子迁移率从8.57 cm²·V^-1·s^-1增至10.46 cm²·V^-1·s^-1,电流开关比提升了一个数量级。此外，超临界处理后器件的光电应力稳定性和光学透明度均得到有效改善。     

激光冲击强化对AZ31B镁合金表面耐腐蚀行为的影响

镁合金具有密度小、比强度和比刚度高、机械加工性能好、生物相容性良好等优异性能，成为潜在新一代可生物降解骨板材料，但其耐腐蚀性能差，限制其发展。使用激光冲击强化技术(LSP),研究其对镁合金表面耐腐蚀性能的影响。采用激光功率密度为1.35 GW/cm²、2.99 GW/cm²和3.92 GW/cm² 进行冲击强化试验，在3.5%(质量分数)NaCl溶液中，通过电化学测量技术动电位扫描得到极化曲线，并通过微观结构探究激光冲击强化对AZ31B镁合金耐腐蚀性能的影响机理。试验结果显示，随着激光功率密度的提升，样品的表面硬度也随之提高，2.99 GW/cm²样品的表面硬度为81.2 HV,相比原始样品提高了35.8%。XRD图谱显示，与原始样品相比，激光冲击处理后的样品衍射峰向高角度方向偏移，衍射峰强度均降低，半峰宽增加。2.99 GW/cm²样品的耐腐蚀性能最好，腐蚀电位为-0.602 41 V,腐蚀电流密度为1.021 5×10^-4 A/cm²     

阳极刻蚀提升Ga2O3肖特基势垒二极管击穿特性

提出了一种采用阳极刻蚀提升Ga₂O₃肖特基势垒二极管(SBD)击穿特性的新方法。基于氢化物气相外延(HVPE)法生长的Ga₂O₃材料制备了Ga₂O₃纵向SBD。在完成阳极制备后，对阳极以外的Ga₂O₃漂移区进行了不同深度的刻蚀，刻蚀完成后，在器件表面生长了SiO₂介质层，随后制备了场板结构。测试结果显示，刻蚀后器件的比导通电阻小幅上升，而反向击穿电压均大幅提升。刻蚀深度为300 nm的β-Ga₂O₃ SBD具有最优特性，其比导通电阻(R_{on, sp})为2.5 mΩ·cm²,击穿电压(V_br)为1 410 V,功率品质因子(FOM)为795 MW/cm²。该研究为高性能Ga₂O₃ SBD的制备提供了一种新方法。     

激光烧蚀辅助激光焊接的焊缝气孔率抑制研究

激光烧蚀辅助的激光焊接可以调节气孔率,进一步提高抗拉强度。在优选焊接参数后,研究了激光烧蚀密度对表面氧含量和表面形貌的影响。0 J/cm²时,表面氧含量(体积分数,下同)为8.91%,表面较为平整。激光烧蚀后,氧含量先减少后增加。8.75 J/cm²时,氧含量为2.75%,仅为0 J/cm²的30.86%,且形成了均匀的火山坑形貌。之后,过高的能量引起热氧化和不规则的烧蚀形貌。用σ_a和σ_b分别作为等离子体/金属蒸气喷发和熔池波动的标准偏差进行定量分析。σ_a和σ_b在0 J/cm²时为0.173和0.045。8.75 J/cm²时,分别为0.176和0.049,最接近0 J/cm²。35 J/cm²时则相反。0 J/cm²时,发现了大量的气孔,气孔率为1.85%。分析了在匙孔和熔池行为影响下三类气孔形成位置。8.75 J/cm     

退火处理降低AlGaN/GaN台面隔离电流

针对电感耦合等离子体(ICP)干法刻蚀后,AlGaN/GaN台面区域存在隔离电流高的问题,研究了不同退火氛围、时间、温度对台面隔离电流的影响。利用原子力显微镜(AFM)和X射线光电子能谱(XPS)及电学测量仪器对样品进行表征和测试。测试结果表明,在氧气和氮气氛围退火处理均能降低样品的隔离电流,且经退火处理后样品的隔离电流均处于10^-9 A/mm数量级,但在氧气氛围中退火处理会使样品的欧姆接触电阻增大。在氮气氛围下的最佳退火处理条件为400℃、120 s。在该条件下样品经过退火处理后,在200 V直流偏压下测得样品的台面隔离电流仅为4.03×10^-9 A/mm,与未经退火处理的样品相比降低了4个数量级,而且在高温测试中样品的隔离电流仍然能够保持较低的数值。     

重掺杂p型SiC晶片Ni/Al欧姆接触特性

系统研究了Al和Ni/Al两种金属体系在重掺杂p型SiC晶片上的欧姆接触特性和电学性质。利用X射线衍射、扫描电子显微镜和综合物性测量系统对这两种电极表面的微观结构和样品的电学性质进行了表征。结果表明：在真空环境下经过800℃退火后Al电极可呈现出欧姆接触行为,其比接触电阻率为1.98×10^-3Ω·cm²,退火处理后Al电极与SiC在接触界面形成化合物Al₄C₃,有助于提高接触界面稳定性。在Ni/Al复合体系中,当Ni金属层厚度为50 nm时,其比接触电阻率显著降低至4.013×10^-4Ω·cm²。退火后Ni与SiC在接触界面生成的Ni₂Si有利于欧姆接触的形成和降低比接触电阻率。研究结果可为开发液相法生长的p型SiC晶片电子器件提供参考。     

长波碲镉汞材料表面的氢化处理研究

本文基于ICP方法对长波HgCdTe材料表面进行了氢化处理,首次在同一焦平面器件上实现了氢化工艺效果的对比.利用原子力显微镜(AFM)、低温探针台系统和焦平面测试系统对HgCdTe材料表面微观形貌及相关器件的电学特性进行了表征分析,结果表明:对长波HgCdTe材料表面进行氢化处理能有效降低MIS器件的界面态、改善二极管器件性能,同时能够增大焦平面器件的信号响应度、减小盲元率.该研究对改善长波HgCdTe/钝化层的界面态以及提高长波HgCdTe器件性能提供了依据.     

Effects of deliberate copper contamination from the platingsolution on the electrical characteristics of MOSFETs

N-channel and p-channel metal-oxide-semiconductor (MOS) transistors of various (W/L) ratios down to 0.24-μm channel length have been used to investigate the effects of deliberate backside copper (Cu) contamination on the MOS field-effect transistor (MOSFET) electrical parameters. The backside of the wafer was flooded with copper sulphate (CuSO₄) solution and air-dried. High-temperature annealing was carried out to drive Cu into silicon. It was discovered that the backside Cu contamination did not result in any undesirable effects on the MOS device performance. The MOS device parameters such as threshold voltage V_TO, transconductance G_m, drain saturation current I_DSAT, off-current I_off, and junction leakage current for n⁺/p and p+/n diodes displayed no significant degradation, even after 5 h of annealing at 400°C in nitrogen ambient. Secondary ion mass spectroscopy data shows that Cu diffused into silicon only over a short distance, leading to little or no degradation of MOSFETs and junction diodes     

用单片清洗设备进行晶圆背面清洗

晶圆背面的污染降低了半导体器件的成品率,而当器件进入100nm技术节点之后成品率的降低便显得尤为重要。因此,目前众多的器件制造厂家就要求在进行片子正面清洗的同时对其背面也能够实现清洗。由Akrion公司制造的Mach2HP系统就是这样一种单片清洗设备,它具有清洗晶圆正反两面的功能。在起初评价时,设备经过了大量的粒子去除效率的变化。这种大量的变化使我们不能了解这种设备真实的清洗能力。氮化硅(Si3N4)粒子污染的晶片被用以进行粒子去除效率测试。我们发现有Si3N4粒子的晶片引起了背面粒子去除效率的变化。这种含Si3N4粒子的晶片是通过在裸芯片上沉积Si3N4粒子而特意准备的。我们发现,一些较大的Si3N4粒子在晶片清洗时又分解成更小的粒子。如若在清洗之后分解的粒子仍保留在晶片上,它们便会降低晶片总的粒子去除效果。因此,在这些粒子沉积到晶片上之前,这些粒子群需要进一步分解成实际的粒子。经过了解晶片的预习处理,我们实现了这种清洗设备背面清洗效果的评价。     

A new laser-processed polysilicon TFT architecture

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm²/Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents     

High-temperature annealing of (\begin{document}${\bar{\mathbf{2}}}{\mathbf{01}}$\end{document}) β-Ga2O3 substrates for reducing structural defects after diamond sawing

A commercial epi-ready (\begin{document}$ {\bar 2}01 $\end{document}) β-Ga₂O₃ wafer was investigated upon diamond sawing into pieces measuring 2.5 × 3 mm². The defect structure and crystallinity in the cut samples has been studied by X-ray diffraction and a selective wet etching technique. The density of defects was estimated from the average value of etch pits calculated, including near-edge regions, and was obtained close to 10⁹ cm⁻². Blocks with lattice orientation deviated by angles of 1−3 arcmin, as well as non-stoichiometric fractions with a relative strain about (1.0−1.5) × 10⁻⁴ in the [\begin{document}$ {\bar 2}01 $\end{document}] direction, were found. Crystal perfection was shown to decrease significantly towards the cutting lines of the samples. To reduce the number of structural defects and increase the crystal perfection of the samples via increasing defect motion mobility, the thermal annealing was employed. Polygonization and formation of a mosaic structure coupled with dislocation wall appearance upon 3 h of annealing at 1100 °C was observed. The fractions characterized by non-stoichiometry phases and the block deviation disappeared. The annealing for 11 h improved the homogeneity and perfection in the crystals. The average density of the etch pits dropped down significantly to 8 × 10⁶ cm⁻².     

Electron microprobe analysis of impurity heterogeneities in thermally grown silicon oxide

The electron probe X-ray microanalyzer is a powerful tool for studying impurity distribution and motion in thin films. This analytical instrument is capable of detecting metallic impurities present in areas as small as 1 × 10^-6mm²and in concentrations of greater than 1 × 10¹⁹atoms/cm³. The analysis requires no sample preparation and is essentially a nondestructive test. This instrument was used to examine unoxidized and oxidized silicon surfaces and a finished microcircuit. With the electron microprobe, aluminum-bearing regions approximately one microns in diameter were detected on the bare surface of mechanically polished silicon slices. These aluminum-rich regions are believed to be alumina abrasive used in polishing. If these regions are not removed by chemical etching they will generate oxide defects during oxidation. These defects were found to contain Al (1 × 10²¹atoms/cm³and Na (1 × 10²⁰atoms/cm³). Other oxide defects, i.e., pinholes, generated during oxidation varied in size from 0.5 to 5.0 microns and were found to contain Na (1×10²¹atoms/cm³) and K (5×10²¹atoms/cm³). Mg and Ca (1 × 10²⁰atoms/cm³) were occasionally observed in these defects. After oxidation, all these impurities could be removed with a hot hydrochloric acid and deionized water rinse; surprisingly, this treatment reduced the silicon surface charge in the MOS structure (X_{0} cong 1500Å) by approximately 1.4 × 10¹¹charges/cm². The surface charge could be further reduced by heating the oxidized wafer at 900°C in a silicon nitride tube.     

Fabrication of carbon nanomaterials by atmospheric pressure microplasma

Atmospheric pressure microplasma was produced in a scanning electron microscope (SEM) chamber for synthesising carbon nanomaterials. The SEM observation is convenient for both adjusting the gap length and observing the electrode surface before and after experiments. After adjusting the gap length, the electrodes were housed in a small removable gas cell equipped in the SEM chamber and CH₄ discharge gas was introduced into the gas cell. It was found that the discharge was pulsated automatically because of slow discharge through a large ballast resistor and fast discharge through gas breakdown, even though a DC voltage was applied. The peak pulse current density was almost 60 kA/cm², the peak power density in the microplasma volume was approximately 555 MW/cm³ and the pulse width was 10 ns typically. Spherical and nanotube-like carbon nanomaterials were found on the cathode surface after microplasma discharge for 1? 5 s.With the discharge time increasing, the spherical substance changes into nanotube-like carbon nanomaterials.     

Composite Spreader for Cooling Computer Chip With Non-Uniform Heat Dissipation

The performance of a composite spreader, with a 0.4 mm thick top layer of porous graphite (PG), for enhanced cooling with nucleate boiling of FC-72 dielectric liquid, and a 1.6 mm copper (Cu) substrate, for achieving better cooling of underlying 10 X 10 mm computer chip, with a non-uniform surface heat flux, is investigated. This spreader takes an advantage of the enhanced nucleate boiling heat transfer of FC-72 dielectric liquid on PG and the good heat spreading by Cu. The dissipated thermal power by the chip has a cosine-like distribution with a peak-to-average heat flux, Phi_max, which varied up to 2.467. The spreader surface area, the total thermal power dissipated by the chip, removed from the surface of the spreader, and the total thermal resistance are calculated and compared with those of PG and Cu spreaders of same thickness, 2.0 mm. With Phi_max = 2.467, 39.48 W and 72.0 W can be removed from the surface of composite spreaders cooled with saturation and 30 K subcooled boiling, compared to 43.0 and 65.3 W for Cu spreaders. The calculated surface areas and total thermal resistances of the composite spreaders, 6.82 cm² and 4.90 cm² and 0.284 and 0.68degC/W, are smaller than for Cu spreaders, 12.26 cm² and 11.92 cm², and 0.51 and 0.83degC/W. In addition, the calculated chip maximum surface temperatures of 62.37degC and 72.2degC, are lower than with Cu spreaders (72.67degC and 76.30degC).     

Reduction in minority carrier storage effect by fluorine ion implantation damage

Damage is produced in p-n diodes by fluorine ion implantation to reduce minority carrier storage effect. The switching time, reverse leakage current, andI-Vcharacteristics were investigated for annealing temperature between 450°C and 650°C. The accelation energy is 130 keV and doses are 10¹³-10¹⁵/cm². Annealing causes restoration in switching time, but leakage current increases with annealing temperature rise for doses more than 1 × 10¹⁴/cm². The best diodes indicate 1.5-order reduction in switching time and 10 nA in reverse leakage current. These properties, caused by implantation damage, are retained after long-cycle annealing at 450°C and are expected to be stable under practical use. These diodes can be obtained by annealing at 450°C and they furnish satisfactory diode performance.     

Si1-x-yGexCy-channel p-MOSFET'swith improved thermal stability

We report the fabrication of heterostructure Si_1-x-yGe _xC_y channel p-MOSFETs with low-carbon Si_1-x-y Ge_xC_y channels. The use of low carbon mole fraction (y=0.002) has only a small effect (≪kT) on the valence band offset. A carbon mole fraction of this value improves the thermal stability of the channel region and makes it possible to use conventional thermal oxidation and ion implant annealing without causing layer relaxation. A peak room-temperature hole mobility of 200 cm² /Vs was measured in a device with a 30-nm channel and a germanium mole fraction ramped from 10% to 40%     

KrF excimer laser annealed TFT with very high field-effect mobilityof 329 cm2/V-s

A thin-film transistor (TFT) with a maximum field-effect mobility of 320 cm²/V-s, an on/off current ratio of 7.6×10⁷ , a threshold voltage of 6.7 V and a subthreshold slope of 0.37 V/decade was fabricated by using pulse laser annealing processes. Amorphous silicon films (a-Si:H) with a very low impurity concentration of 4×10¹⁸ cm^-3 for oxygen, 1.5×10¹⁸ cm^-3 for carbon, and 2×10¹⁷ cm^-3 for nitrogen were deposited by a plasma chemical vapor deposition (CVD) method and annealed by KrF excimer laser (wavelength of 248 nm). The Raman spectroscopy technique was a useful tool for optimizing laser annealing conditions. Experimental results show that two factors are very important for fabricating very-high mobility TFTs: (1) utilizing high-purity as-deposited a-Si:H film; and (2) performing whole laser annealing processes sequentially in a vacuum container and optimizing illumination conditions