LCCC封装器件热疲劳失效分析及结构优化研究

针对LCCC封装器件在温度循环载荷下焊点开裂的问题,首先分析其失效现象和机理,并建立有限元模型,进行失效应力仿真模拟。为降低焊点由封装材料CTE不匹配引起的热应力,提出了两种印制板应力释放方案,并分析研究单孔方案中不同孔径和阵列孔方案中不同孔数量对热疲劳寿命的影响。之后,为降低对PCB布局密度的影响,提出一种新型的叠层焊柱应力缓冲方案,进行了不同叠层板厚度和焊柱间距的敏感度分析。结果表明,更大的开孔面积、更小的叠层板厚度、更密的焊柱可有效降低焊点应力,提高焊点热疲劳寿命,使得LCCC封装器件焊点热疲劳可靠性得到有效提高。     

工业级FPGA空间应用器件封装可靠性分析

分析了工业级和宇航级FPGA(Field Programmable Gate Array)在封装结构上的差别。用Ansysworkbench有限元软件对热循环、随机振动和外力载荷下封装的变形和应力以及焊点的塑性应变进行了仿真。依据剪切塑性应变变化范围预测了焊点热疲劳寿命。结果表明,FCBGA(Flip-Chip Ball Grid Array)封装内部倒装芯片焊点可靠性低于CCGA(Ceramic Column Grid Array)封装,其外部焊点的热疲劳寿命、随机振动等效应力均优于CCGA封装;在外力载荷下,其热疲劳寿命下降速率也明显小于CCGA封装。     

随机振动下板级组件焊点可靠性研究进展

针对板级组件焊点在随机振动下的可靠性问题,对与之相关的实验研究成果和仿真结果进行了综述。首先介绍了球栅阵列(BGA)封装芯片焊点失效的位置,BGA焊点的材料以及BGA参数和印制电路板(PCB)参数对焊点可靠性的分析,并介绍了疲劳寿命预测方法和子模型法、特殊结构的随机振动分析。最后,提出了随机振动情况下的BGA结构的优化方法。     

PBGA组件振动疲劳寿命的实验研究

为了得到在基频激励下PBGA封装的可靠度特性,设计制作了一块包含不同结构和材料参数的PBGA组件样品,利用可靠性实验的方法测试了PBGA组件在正弦单频激励条件下的疲劳特性,同时运用Manson-Coffin方程经验公式及雨流计数法得到了相对应的焊点疲劳寿命.最后利用疲劳统计中威布尔分布得到了当PBGA芯片位于PCB不同位置、不同激励时可靠度-循环失效圈数曲线(R-N曲线).结果表明,大直径焊点芯片、分布在约束较多PCB上的芯片、无铅焊点芯片的焊点可靠度较高.     

基于FCBGA封装应用的有机基板翘曲研究

有机基板作为IC封装的重要载体,其制造材料的特性对封装工艺的稳定性及可靠性有重要影响。针对倒装芯片球栅阵列（FCBGA）有机基板在再流焊过程中的翘曲问题,使用热形变测试仪研究了不同尺寸和芯板厚度的有机基板在再流焊过程中的共面性及形变情况,研究FCBGA有机基板的翘曲行为。针对大尺寸FCBGA有机基板在再流焊过程中的翘曲问题,从脱湿、夹持载具以及再流焊曲线优化等方面提出改善措施,为FCBGA有机基板的封装应用提供参考。     

PBGA封装焊点寿命影响因素的有限元分析

为明确PBGA焊点设计及环境温度参数对其可靠性影响,利用有限元软件ANSYS分析了温度循环、焊点材料、焊点高度与直径、PCB板的厚度、刚度、热膨胀系数(CTE)对焊点寿命的影响.焊点采用了Anand本构关系描述,寿命预测采用Darveaux模型.研究结果表明,温度循环的范围变大焊点寿命变短,保温时间缩短能增加焊点寿命;经过优化的焊球,寿命会增加;PCB板越厚,焊点寿命越短;PCB板的杨氏模量越大,焊点寿命越长.     

芯片级封装与HDI/BUM板

芯片级封装是指芯片在PCB基板上安装尺寸等于或接近于芯片尺寸的、高密度组装技术,它是在表面安装技术上深入发展起来而成为新一代的电路组装技术。芯片级封装的优点使它成为当前和今后最具优势(选)的高密度封装方法之一。而HDI/BUM 板是受芯片级封装技术推动而发展起来新一代PCB产品。HDI/BUM 板将推动PCB全面走向高密度化(微导通孔、导线微细化、介质薄型化等),严格的 CTE匹配和紧密的板面高平整度化要求,最后介绍了 HDI/BUM的关键生产工艺。     

化学镍金基板焊点的失效分析

硅麦克风在消费类电子产品中成功应用,近年来得到了迅猛发展。硅麦克风的封装工艺由于MEMS的特殊结构和封装材料的特殊性,与常见IC封装有许多不同点。其中引线键合工序由于所使用的PCB基板材料特殊的加工工艺,使得引线在PCB基板上的焊点失效成为研究硅麦克风封装成品率和可靠性的一个重要课题。文章重点探讨了硅麦克风封装过程中引线键合工序焊点失效问题,通过不同金线键合方式和金线键合参数的分析,确立了适合于硅麦克风封装的金线键合工艺。     

弯曲应力状况下微型BGA封装可靠性比较研究

微型球栅阵列（μBGA）是芯片规模封装（CSP）的一种形式,已发展成为最先进的表面贴装器件之一。在最新的IxBGA类型中使用低共晶锡．铅焊料球,而不是电镀镍金凸点。采用传统的表面贴装技术进行焊接,研讨μBGA的PCB装配及可靠性。弯曲循环试验（1000～1000με）,用不同的热因数（Qη）回流,研究μBGA、PBGA和CBGA封装的焊点疲劳失效问题。确定液相线上时间,测定温度,μBGA封装的疲劳寿命首先增大,接着随加热因数的增加而下降。当Q。接近500S·℃时,出现寿命最大值。最佳Qη范围在300-750s·℃之间,此范围如果装配是在氮气氛中回流,μBGA封装的寿命大于4500个循环。采用扫描电子显微镜（SEM）,来检查μBGA和PBGA封装在所有加热N数状况下焊点的失效。每个断裂接近并平行于PCB焊盘,在μBGA封装中裂纹总是出现在焊接点与PCB焊盘连接的尖角点,接着在Ni3Sn4金属间化合物（IMC）层和焊料之间延伸。CBGA封装可靠性试验中,失效为剥离现象,发生于陶瓷基体和金属化焊盘之间的界面处。     

倒装芯片焊点可靠性的有限元模拟法综述

随着集成电路封装技术的发展,倒装芯片技术得到广泛的应用。由于材料的热膨胀失配,使倒装焊点成为芯片封装中失效率最高的部位,而利用快捷又极具参考价值的有限元模拟法是研究焊点可靠性的重要手段之一。介绍了集成电路芯片焊点可靠性分析的有限元模拟法,概括了利用该方法对芯片焊点进行可靠性评价常见的材料性质和疲劳寿命预测模型。     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Solder Joint Reliability Assessment for Flip Chip Ball Grid Array Components with Various Designs in Lead-Free Solder Materials and Solder Mask Dimensions

This study investigates the reliability of flip chip ball grid array (FCBGA) components with three types of solder materials: eutectic solder with a composition Sn63Pb37 and the lead-free solders SnAg3.0Cu0.5 and SnAg4.0Cu0.5. Two substrate-side solder mask (S/M) opening sizes, 0.4 mm and 0.525 mm, were used. Both the monotonic and cyclic mechanical four-point bend tests are conducted for the reliability assessment. It is found that the FCBGA components with SnAg3.0Cu0.5 solder have the best durability during the cyclic bend test, yet the eutectic solder is the strongest during the monotonic bend test. Besides, the FCBGA components with 0.525-mm S/M opening have around 3 times more life cycles than those with the 0.4-mm S/M opening in the cyclic bend test. It is also noteworthy that the lead-free solder materials have much variation in the failed cycles during the cyclic test. Moreover, the failure locations for those components with 0.4-mm S/M openings are found to be at the interface between the package side metal pad and the solder ball, and those with an S/M opening of 0.525 mm are observed to be failed mostly at the interface between the printed circuit board (PCB) side metal pad and the solder ball.     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests.     

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

基于稳健设计的PBGA器件焊点热机械疲劳可靠性的优化设计

基于稳健设计与有限元法,研究了加速热循环测试条件下塑封球栅阵列(PBGA)焊点的热机械疲劳可靠性.考虑PCB大小(A)、基板厚度(D)、硅片热膨胀系数(G)、焊点热膨胀系数(H)等八个控制因素,使用L₁₈(2¹×3⁷)混合正交表,以对焊点热机械疲劳寿命的考核为目标,对PBGA焊点进行了优化设计.结果表明,影响焊点可靠性的显著性因素依次是基板热膨胀系数、焊点的热膨胀系数、基板厚度、芯片的热膨胀系数;最优方案组合为A1B2C3D1E2F1G3H1.进一步的验证试验结果表明,与原始方案相比,该优化方案的最大等效应变降低了66%,信噪比提高了22.4％.