TFT-LCD驱动芯片的二级驱动电路

针对单芯片集成的TFT-LCD驱动芯片的特性,提出了在γ校正电路中加入两级驱动Buffef的驱动电路结构,以及提高其驱动能力的有效措施.对于具有13个驱动buffer的二级驱动电路,当由一个灰度电压驱动全部396个像素单元时,驱动电压的最大安定时间约为19.2μs;静态消耗电流为518μA,与传统的64个驱动buffer电路相比,其功耗减小了77%.本文的设计结果已成功应用于132RGB×176分辨率、26万色彩色显示手机用TFT-LCD驱动芯片中,其也可用于PDA、数码相机等其他便携电子设备的显示驱动.     

中小屏幕TFT-LCD驱动芯片的输出缓冲电路

在分析中小屏幕TFT-LCD驱动芯片的负荷特性的基础上,提出了一种新型的驱动电压输出缓冲电路结构.通过负反馈动态控制输出级的工作状态,具有交替提供拉电流和灌电流的驱动能力,可有效抑制输出电压的波动.与传统的两级运算放大器电路相比,该电路结构简单,稳定性能好,降低了静态功耗并节省了芯片面积.采用0.25μm CMOS工艺设计并实现了两种不同输出电压的缓冲电路.HSPICE仿真结果表明,输出电压缓冲电路的静态电流为3μA,Offset电压小于±2mV.同时,当TFT-LCD的驱动电压在-8～ 16V之间切换时,输出电压的波动范围小于±0.4V,输出电压的恢复时间小于7μs.经对工程样片的测试知,其性能完全满足中小屏幕TFT-LCD驱动控制芯片的要求.     

中小屏幕TFT-LCD驱动芯片的输出缓冲电路

在分析中小屏幕TFT-LCD驱动芯片的负荷特性的基础上,提出了一种新型的驱动电压输出缓冲电路结构.通过负反馈动态控制输出级的工作状态,具有交替提供拉电流和灌电流的驱动能力,可有效抑制输出电压的波动.与传统的两级运算放大器电路相比,该电路结构简单,稳定性能好,降低了静态功耗并节省了芯片面积.采用0.25μm CMOS工艺设计并实现了两种不同输出电压的缓冲电路.HSPICE仿真结果表明,输出电压缓冲电路的静态电流为3μA,Offset电压小于±2mV.同时,当TFT-LCD的驱动电压在-8～+16V之间切换时,输出电压的波动范围小于±0.4V,输出电压的恢复时间小于7μs.经对工程样片的测试知,其性能完全满足中小屏幕TFT-LCD驱动控制芯片的要求.     

TFT-LCD驱动芯片内置电源产生模块设计

从中小屏幕TFT-LCD的显示和驱动原理出发,设计了一种用于TFT-LCD驱动IC的内置电源产生模块。该模块为芯片中各个数字和模拟子系统提供基准电压、偏置电压、工作电压和TFT-LCD的驱动电压。针对芯片各模块的负载和对供电电压的不同要求,提出了一种以带隙基准电路为核心,由LDO电路、电荷泵电路等组成的电源模块的系统解决方案。通过0.25μmCMOS高压工艺的HSPICE仿真及工程样片流片验证,证明此设计能够满足TFT-LCD驱动芯片的性能指标要求。     

TFT-LCD驱动芯片内置电源电路IP核设计

设计了一种采用0.25μm CMOS低压/中压/高压混合电压工艺的TFT-LCD驱动芯片内置电源电路IP核.该IP模块包括低压降线性稳压电路、电荷泵升压/反压电路、VCOM驱动电路和VGOFF驱动电路等,能够提供驱动芯片的系统工作电压和TFT-LCD的驱动电压.所产生的电压值可实现编程控制,具有启动时间快、工作稳定和较低的温度系数等特点.仿真与测试结果表明,在上电200ms后能够生成稳定、正确的输出电压.电源电路模块的总静态功耗小于2mW.     

TFT-LCD驱动芯片内置电源电路IP核设计

设计了一种采用0.25μm CMOS低压/中压/高压混合电压工艺的TFT-LCD驱动芯片内置电源电路IP核.该IP模块包括低压降线性稳压电路、电荷泵升压/反压电路、VCOM驱动电路和VGOFF驱动电路等,能够提供驱动芯片的系统工作电压和TFT-LCD的驱动电压.所产生的电压值可实现编程控制,具有启动时间快、工作稳定和较低的温度系数等特点.仿真与测试结果表明,在上电200ms后能够生成稳定、正确的输出电压.电源电路模块的总静态功耗小于2mW.     

手机用TFT-LCD驱动控制芯片电源模块设计

电源模块是TFT-LCD驱动控制芯片内置模拟电路的一个重要组成部分,其性能直接影响着芯片的功耗以及彩屏手机的显示画质。文章从TFT-LCD的驱动原理出发,提出了一种低功耗、易调节的电源模块设计思想,所产生的电压值可实现编程控制。用Hspice对采用0.25μmCMOS工艺设计的电路进行仿真表明,系统在启动200ms后能够生成稳定、正确的驱动电源电压,其静态功耗小于2mW。     

手机用TFT-LCD Source Driver电路模块研究与设计

SourceDriver电路模块是彩色TFT-LCD驱动控制芯片的关键电路之一,其功能是将数字图像显示数据转换成模拟驱动电压,从而驱动TFT-LCD显示各种彩色图像。本文从TFT-LCD的驱动原理出发,提出了一种适合于手机用TFT-LCD的低功耗、小面积的SourceDriver电路体系结构,用0.25μmCMOS工艺设计并实现了显示26万(26×26×26)色,支持132RGB×176分辨率的手机用TFT-LCD驱动控制芯片中的SourceDriver电路,电路面积约15mm×0.6mm。Hspice仿真结果表明,SourceDriver电路的响应时间为1.49μs,静态功耗小于1mW。     

TFT-LCD驱动芯片内置电源电路IP核设计

为了进一步提高TFT-LCD驱动芯片内置电源电路设计的合理性,为薄膜晶体管液晶显示器提供更加优质的电路服务,文章通过对TFT-LCD电源电路模块的功能和结构进行分析,在结合其驱动电压要求的基础上,对其内置电源电路IP核展开了详细的设计和分析。研究结果表明,文章所设计的TFT-LCD驱动芯片内置电源电路的IP核,具有显示时间快和工作稳定等特点,能够较好地对内置电源电路进行驱动。     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。     

26万色TFT-LCD单片集成驱动芯片的Top-Down设计

提出了应用于TFT-LCD单片集成驱动芯片的Top-down设计技术,并成功开发了一款26万色、176RGB×220分辨率的TFT-LCD驱动芯片.该芯片是典型的混合信号超大规模集成电路芯片,采用0.18μm HV CMOS工艺制造.在26万色显示模式下,芯片的静态功耗是5mW,输出驱动电压的建立时间(0.2%误差范围内)小于26pμs.     

手机用彩色TFT-LCD驱动控制芯片的驱动电路设计

目前TFF-LCD彩色液晶显示屏被广泛应用于中高档彩屏手机中。TFT-LCD驱动控制芯片作为手机主机与TFT-LCD显示屏之间的接口电路，控制和驱动显示屏的彩色显示，其性能直接影响着显示画面的质量和系统功耗。文章从TFF-lED的驱动原理出发，提出了手机用26万色彩色TFT-LCD驱动芯片的驱动电路设计方法，包括gamma校正电路，gate driver电路和source driver电路的结构与功能分析，最后给出了Hspiee的仿真结果。     

A 402-output TFT-LCD driver IC with power control based on the number of colors selected

A 402-output thin-film-transistor liquid crystal display (TFT-LCD) driver integrated circuit (IC) with power control based on the number of colors to be displayed is described. To achieve this type of power control, reference voltage buffers are turned on and off according to the selected number of colors. In this architecture, the reference voltage buffers must drive 1-402 capacitive loads, corresponding to a capacitance of 30-12000 pF. Phase compensation using a zero formed with capacitive loads is proposed for the reference voltage buffers. The introduced zero has a fixed zero frequency for 1-402 loads. An operational amplifier with slew-rate enhancement is also proposed for the buffers. An experimental 402-output TFT-LCD driver IC was fabricated using a 0.6-/spl mu/m CMOS technology. The chip size was 2.35 mm /spl times/ 18.1 mm. The quiescent current dissipation of the analog section including decoders was 529 /spl mu/A for 262144 colors, 182 /spl mu/A for 4096 colors, and 112 /spl mu/A for 512 colors for a 5-V supply.     

采用电容延时和反馈的抑制毛刺复位接口电路

针对手机用TFT-LCD驱动控制芯片的应用环境具有高噪声、毛刺持续时间长的特点,提出一种采用电容充放电延时和反馈技术的抑制毛刺复位接口电路。该电路可以消除持续时间长达数微秒的单个毛刺。另外,通过自动选择不同的充放电路径,可实现不同的延迟时间,从而可以消除毛刺的累积效益。设计的复位接口电路已经成功应用于176RGB×220分辨率、26万色手机用TFT-LCD驱动控制芯片。采用0.18μmCMOS中压工艺的HSPICE仿真以及工程样片流片结果表明,所设计的复位接口电路的性能完全满足TFT-LCD驱动控制芯片的复杂应用环境要求,并且具有面积开销较小的特点。     

An efficient driving method for a high-voltage CMOS driver IC

An efficient driving method for a high-voltage CMOS driver integrated circuit (IC) is proposed. It utilises an auxiliary circuit to reduce the voltage across the data driver IC when its output stages change their status. The auxiliary circuit can reduce the power consumption and relieve the thermal problems of the driver ICs. Moreover, it has load adaptive characteristics. Power consumption was reduced by 46% at one dot on/off image pattern.     

应用于可携式产品液晶显示器之低靜态电流与晶片面积的源极驱动电路架构

在这篇论文中,我们提出一种适用于 QCIF 解析度、262千色的薄膜电晶体液晶显示器,具有低静态电流和晶片面积的源极驱动电路架构.此类驱动晶片可以实际被应用于行动电话或其他高阶可攜式电子产品上.传统A、B、C等三种形式的源极驱动电路,需使用大量的运算放大器来驱动面板中的画素,和较大阻值的电阻式数位类比转换电路来产生珈玛电压,以保有最低的静态消耗电流.而我们提出的第四种源极驱动电路架构,仅使用二个运算放大器和较低电阻的电阻式数位类比转换电路,而且并不会增加静态消耗电流.因此,这颗源极驱动晶片,不仅可省下晶片面积、增加产品竞爭力,更可以降低静态功率的消耗以延长电池的续航力.我们所提出的运算放大器和源极驱动电路之原型晶片,是利用 3.3 V、0.35 μm ACMOS的制程技术来实现的.运算放大器电路的核心尺寸大小为 100 μm×50 μm,源极驱动电路为 400 μm×650 μm.由我们所提出的第四种驱动电路架构,晶片面积约可减少 54.25%,而静态消耗电流仅需 2.6%.     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

Design and analysis of a low-swing driver scheme for long interconnects

Market forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. The paper describes the design of a low-swing signalling scheme which consists of a low-swing driver, called the nLVSD driver which is an improved version of the MJ-driver [1] designed by Juan A. Montiel-Nelson and Jose C. Garcia. Subsequently, both low-swing driver schemes are analysed and compared focusing on their power consumption and performance characteristics, which are the main issues in present day IC design. A comparison between the two driver schemes showed that the nLVSD driver exhibited a 34% improvement regarding power consumption and a 28% improvement in delay when driving a 10 mm length of interconnect. A comparison between the two schemes was also undertaken in the presence of ±3σ Process and Voltage (PV) variations. The analysis indicated that the nLVSD driver scheme was more robust than the MJ-driver with a 33% and 44% improvement with respect to power consumption and delay variations. In order to further improve the robustness of the nLVSD scheme against process variation, the scheme was further analysed to identify which process variables had the most impact on circuit delay and power consumption. For completeness the effects of process variation on interconnect delay and power consumption was also undertaken.     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.