Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

AlGaN/GaN HEMT泄漏电流的退化研究

针对AlGaN/GaN HEMT器件在寿命试验过程中经常出现的栅源、栅漏和源漏泄漏电流随试验时间的延长而增大的现象,展开了深入的研究.分析了当前HEMT器件泄漏电流的各种主流退化模型,通过试验发现热载流子效应、逆压电效应等难以完全解释泄漏电流间的退化差异.进一步的研究显示,电极间的泄漏电流的差异主要是由材料中的缺陷和陷阱的密度分布不均匀造成的.在应力的作用下,初始密度越大,试验过程中缺陷和陷阱的增长速度就越快,泄漏电流的增长速度也就越快.但应力撤除后,由陷阱辅助隧穿导致的泄露电流会逐渐地得到恢复.     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究.分析表明,在TLP应力下,栅串接电阻减小了保护结构漏端的峰值电压;栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场,栅氧化层电场随着TLP应力的上升沿减小而不断增大,这会导致栅氧化层的提前击穿.仿真显示,栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的.该工作为以后的TLP测试和标准化提供了依据和参考.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究. 分析表明，在TLP应力下，栅串接电阻减小了保护结构漏端的峰值电压；栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场，栅氧化层电场随着TLP应力的上升沿减小而不断增大，这会导致栅氧化层的提前击穿. 仿真显示，栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的. 该工作为以后的TLP测试和标准化提供了依据和参考.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hot-carrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性.测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移,并与单独HCI和NBT应力下的特性进行了对比.在这两种应力偏置条件下,pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强.由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场,使得器件特性严重退化.给出了NBT效应不断增强的HCI耦合效应的详细解释.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

超薄栅氧化物pMOSFET器件在软击穿后的特性

研究了在软击穿后MOS晶体管特性的退化.在晶体管上加均匀的电压应力直到软击穿发生的过程中监控晶体管的参数.在软击穿后,输出特性和转移特性只有小的改变.在软击穿发生时,漏端的电流和域值电压的退化是连续变化的.但是,在软击穿时栅漏电流突然有大量的增加.对软击穿后的栅漏电流增量的分析表明,软击穿后的电流机制是FN隧穿,这是软击穿引起的氧化物的势垒高度降低造成的.     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure     

A comprehensive study of hot carrier stress-induced drain leakagecurrent degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V_gs such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 Å) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 Å) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation     

A model for n-well junction effect on gate-charging damage inPMOSFETs

A quantitative model explaining N-well junction effect on gate charging damage in PMOSFETs is presented. This model takes into account the reverse-biased N-well junction leakage, generated both thermally and by photons and its behavior on limiting charging current passing through gate oxide during plasma processing. The modeling results suggest that plasma illumination plays a key role in enabling gate charging damage in PMOSFETs. The model can also apply to reverse-biased source and drain junctions in both P and NMOSFETs during plasma events     

Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thin-film transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.